Searched refs:NEG_D (Results 1 - 9 of 9) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 446 NEG_D = 4, enumerator
1102 return Latency::NEG_D; in NegdLatency()
1105 return CompareIsNanF64Latency() + 2 * Latency::BRANCH + Latency::NEG_D + in NegdLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 419 NEG_D = 4, enumerator
1185 return Latency::NEG_D; in Neg_dLatency()
1188 return CompareIsNanF64Latency() + 2 * Latency::BRANCH + Latency::NEG_D + in Neg_dLatency()
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 447 NEG_D = 4, enumerator
965 return CompareIsNanF64Latency() + 2 * Latency::BRANCH + Latency::NEG_D + in NegdLatency()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 689 NEG_D = ((0U << 3) + 7),
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| H A D | assembler-mips64.cc | 2900 GenInstrRegister(COP1, S, f0, fs, fd, NEG_D); in neg_s()
2904 GenInstrRegister(COP1, D, f0, fs, fd, NEG_D); in neg_d()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 644 NEG_D = ((0U << 3) + 7),
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| H A D | assembler-mips.cc | 2629 GenInstrRegister(COP1, D, f0, fs, fd, NEG_D); in neg_d()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3207 case NEG_D: in DecodeTypeRegisterDRsType()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 2826 case NEG_D: in DecodeTypeRegisterDRsType()
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