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/third_party/skia/experimental/graphite/src/
H A DEnumBitMask.h29 * Mask<MyFlags> flags = MyFlags::kA | MyFlags::kB;
36 class Mask { class
38 SK_ALWAYS_INLINE constexpr Mask(E e) : Mask((int)e) {} in Mask() function in skgpu::Mask
42 SK_ALWAYS_INLINE bool operator==(Mask m) const { return fValue == m.fValue; } in operator ==()
43 SK_ALWAYS_INLINE bool operator!=(Mask m) const { return fValue != m.fValue; } in operator !=()
45 SK_ALWAYS_INLINE constexpr Mask operator|(Mask m) const { return Mask(fValue | m.fValue); } in operator |()
46 SK_ALWAYS_INLINE constexpr Mask operato in operator |()
55 SK_ALWAYS_INLINE constexpr explicit Mask(int value) : fValue(value) {} Mask() function in skgpu::Mask
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/third_party/node/deps/v8/src/codegen/arm64/
H A Ddecoder-arm64-inl.h141 (instr->Mask(0x01000010) == 0x00000010)) { in DecodeBranchSystemException()
155 (instr->Mask(0x00E0001D) == 0x00200001) || in DecodeBranchSystemException()
156 (instr->Mask(0x00E0001D) == 0x00400001) || in DecodeBranchSystemException()
157 (instr->Mask(0x00E0001E) == 0x00200002) || in DecodeBranchSystemException()
158 (instr->Mask(0x00E0001E) == 0x00400002) || in DecodeBranchSystemException()
159 (instr->Mask(0x00E0001C) == 0x00600000) || in DecodeBranchSystemException()
160 (instr->Mask(0x00E0001C) == 0x00800000) || in DecodeBranchSystemException()
161 (instr->Mask(0x00E0001F) == 0x00A00000) || in DecodeBranchSystemException()
162 (instr->Mask(0x00C0001C) == 0x00C00000)) { in DecodeBranchSystemException()
169 const Instr masked_003FF0E0 = instr->Mask( in DecodeBranchSystemException()
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H A Dinstructions-arm64.h108 Instr Mask(uint32_t mask) const { return InstructionBits() & mask; } in Mask() function in v8::internal::Instruction
147 return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask))); in SizeLS()
152 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask))); in SizeLSPair()
165 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed; in IsCondBranchImm()
169 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed; in IsUncondBranchImm()
173 return Mask(CompareBranchFMask) == CompareBranchFixed; in IsCompareBranch()
176 bool IsTestBranch() const { return Mask(TestBranchFMask) == TestBranchFixed; } in IsTestBranch()
208 return Mask(LoadLiteralFMask) == LoadLiteralFixed; in IsLdrLiteral()
211 bool IsLdrLiteralX() const { return Mask(LoadLiteralMask) == LDR_x_lit; } in IsLdrLiteralX()
212 bool IsLdrLiteralW() const { return Mask(LoadLiteralMas in IsLdrLiteralX()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
H A DLaneBitmask.h46 explicit constexpr LaneBitmask(Type V) : Mask(V) {} in LaneBitmask()
48 constexpr bool operator== (LaneBitmask M) const { return Mask == M.Mask; } in operator ==()
49 constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; } in operator !=()
50 constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; } in operator <()
51 constexpr bool none() const { return Mask == 0; } in none()
52 constexpr bool any() const { return Mask != 0; } in any()
53 constexpr bool all() const { return ~Mask in any()
89 Type Mask = 0; global() member
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIModeRegister.cpp40 // Mask is a bitmask where a '1' indicates the corresponding Mode bit has a
42 unsigned Mask; member
45 Status() : Mask(0), Mode(0){}; in Status()
47 Status(unsigned NewMask, unsigned NewMode) : Mask(NewMask), Mode(NewMode) { in Status()
48 Mode &= Mask; in Status()
54 return Status((Mask | S.Mask), ((Mode & ~S.Mask) | (S.Mode & S.Mask))); in merge()
60 return Status(Mask in mergeUnknown()
255 unsigned Mask = ((1 << Width) - 1) << Offset; processBlockPhase1() local
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H A DAMDGPUArgumentUsageInfo.h37 unsigned Mask; member
43 ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u, in ArgDescriptor()
45 : Reg(Val), Mask(Mask), IsStack(IsStack), IsSet(IsSet) {} in ArgDescriptor()
47 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) { in createRegister()
48 return ArgDescriptor(Reg, Mask, false, true); in createRegister()
51 static ArgDescriptor createStack(unsigned Offset, unsigned Mask = ~0u) { in createStack()
52 return ArgDescriptor(Offset, Mask, true, true); in createStack()
55 static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) { in createArg()
56 return ArgDescriptor(Arg.Reg, Mask, Ar in createArg()
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H A DGCNRegBankReassign.cpp78 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
81 unsigned Mask; member in __anon24457::GCNRegBankReassign::OperandMask
192 // Find all bank bits in UsedBanks where Mask can be relocated to.
193 unsigned getFreeBanks(unsigned Mask, unsigned UsedBanks) const;
195 // Find all bank bits in UsedBanks where Mask can be relocated to.
198 unsigned getFreeBanks(unsigned Reg, unsigned SubReg, unsigned Mask,
316 unsigned Mask = (1 << Size) - 1;
323 Mask &= ~Used;
324 Mask <<= (Bank == -1) ? Reg % NUM_VGPR_BANKS : unsigned(Bank);
325 return (Mask | (Mas
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp96 void converted(Instruction *I, Value *V, int Mask, bool Worthy) { in converted() argument
97 ConvertedInsts[I] = std::make_tuple(V, Mask, Worthy); in converted()
204 int Mask = 0; in convertFCmp() local
206 Mask |= Masks[WhichConst][0]; in convertFCmp()
208 Mask |= Masks[WhichConst][1]; in convertFCmp()
210 Mask |= Masks[WhichConst][2]; in convertFCmp()
212 Mask |= Masks[WhichConst][3]; in convertFCmp()
220 Mask &= SystemZ::TDCMASK_PLUS; in convertFCmp()
221 Mask |= Mask >> in convertFCmp()
246 int Mask; convertICmp() local
271 int Mask = MaskC->getZExtValue(); convertICmp() local
295 int Mask; convertLogicOp() local
351 int Mask; runOnFunction() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DScalarizeMaskedMemIntrin.cpp80 static bool isConstantIntVector(Value *Mask) { in isConstantIntVector() argument
81 Constant *C = dyn_cast<Constant>(Mask); in isConstantIntVector()
85 unsigned NumElts = Mask->getType()->getVectorNumElements(); in isConstantIntVector()
130 Value *Mask = CI->getArgOperand(2); in scalarizeMaskedLoad() local
146 if (isa<Constant>(Mask) && cast<Constant>(Mask)->isAllOnesValue()) { in scalarizeMaskedLoad()
164 if (isConstantIntVector(Mask)) { in scalarizeMaskedLoad()
166 if (cast<Constant>(Mask)->getAggregateElement(Idx)->isNullValue()) in scalarizeMaskedLoad()
182 SclrMask = Builder.CreateBitCast(Mask, SclrMaskTy, "scalar_mask"); in scalarizeMaskedLoad()
195 Value *Mask in scalarizeMaskedLoad() local
269 Value *Mask = CI->getArgOperand(3); scalarizeMaskedStore() local
326 Value *Mask = Builder.getInt(APInt::getOneBitSet(VectorWidth, Idx)); scalarizeMaskedStore() local
393 Value *Mask = CI->getArgOperand(2); scalarizeMaskedGather() local
445 Value *Mask = Builder.getInt(APInt::getOneBitSet(VectorWidth, Idx)); scalarizeMaskedGather() local
518 Value *Mask = CI->getArgOperand(3); scalarizeMaskedScatter() local
566 Value *Mask = Builder.getInt(APInt::getOneBitSet(VectorWidth, Idx)); scalarizeMaskedScatter() local
601 Value *Mask = CI->getArgOperand(1); scalarizeMaskedExpandLoad() local
656 Value *Mask = Builder.getInt(APInt::getOneBitSet(VectorWidth, Idx)); scalarizeMaskedExpandLoad() local
715 Value *Mask = CI->getArgOperand(2); scalarizeMaskedCompressStore() local
762 Value *Mask = Builder.getInt(APInt::getOneBitSet(VectorWidth, Idx)); scalarizeMaskedCompressStore() local
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H A DInterleavedAccessPass.cpp142 static bool isDeInterleaveMaskOfFactor(ArrayRef<int> Mask, unsigned Factor, in isDeInterleaveMaskOfFactor() argument
150 for (; i < Mask.size(); i++) in isDeInterleaveMaskOfFactor()
151 if (Mask[i] >= 0 && static_cast<unsigned>(Mask[i]) != Index + i * Factor) in isDeInterleaveMaskOfFactor()
154 if (i == Mask.size()) in isDeInterleaveMaskOfFactor()
166 static bool isDeInterleaveMask(ArrayRef<int> Mask, unsigned &Factor, in isDeInterleaveMask() argument
169 if (Mask.size() < 2) in isDeInterleaveMask()
175 if (Mask.size() * Factor > NumLoadElements) in isDeInterleaveMask()
177 if (isDeInterleaveMaskOfFactor(Mask, Factor, Index)) in isDeInterleaveMask()
195 static bool isReInterleaveMask(ArrayRef<int> Mask, unsigne argument
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/third_party/node/deps/v8/src/diagnostics/arm64/
H A Ddisasm-arm64.cc58 switch (instr->Mask(AddSubImmediateMask)) { in VisitAddSubImmediate()
104 switch (instr->Mask(AddSubShiftedMask)) { in VisitAddSubShifted()
154 switch (instr->Mask(AddSubExtendedMask)) { in VisitAddSubExtended()
193 switch (instr->Mask(AddSubWithCarryMask)) { in VisitAddSubWithCarry()
238 switch (instr->Mask(LogicalImmediateMask)) { in VisitLogicalImmediate()
306 switch (instr->Mask(LogicalShiftedMask)) { in VisitLogicalShifted()
365 switch (instr->Mask(ConditionalCompareRegisterMask)) { in VisitConditionalCompareRegister()
385 switch (instr->Mask(ConditionalCompareImmediateMask)) { in VisitConditionalCompareImmediate()
411 switch (instr->Mask(ConditionalSelectMask)) { in VisitConditionalSelect()
468 switch (instr->Mask(BitfieldMas in VisitBitfield()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp446 SmallVectorImpl<Constant*> &Mask) { in collectSingleShuffleElements()
452 Mask.assign(NumElts, UndefValue::get(Type::getInt32Ty(V->getContext()))); in collectSingleShuffleElements()
458 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), i)); in collectSingleShuffleElements()
464 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), in collectSingleShuffleElements()
482 if (collectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { in collectSingleShuffleElements()
484 Mask[InsertedIdx] = UndefValue::get(Type::getInt32Ty(V->getContext())); in collectSingleShuffleElements()
497 if (collectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { in collectSingleShuffleElements()
500 Mask[InsertedIdx % NumElts] = in collectSingleShuffleElements()
505 Mask[InsertedIdx % NumElts] = in collectSingleShuffleElements()
599 /// left and right vectors of the proposed shuffle (or 0), and set the Mask
445 collectSingleShuffleElements(Value *V, Value *LHS, Value *RHS, SmallVectorImpl<Constant*> &Mask) collectSingleShuffleElements() argument
606 collectShuffleElements(Value *V, SmallVectorImpl<Constant *> &Mask, Value *PermittedRHS, InstCombiner &IC) collectShuffleElements() argument
1082 SmallVector<Constant*, 16> Mask; visitInsertElementInst() local
1126 canEvaluateShuffled(Value *V, ArrayRef<int> Mask, unsigned Depth = 5) canEvaluateShuffled() argument
1289 evaluateInDifferentElementOrder(Value *V, ArrayRef<int> Mask) evaluateInDifferentElementOrder() argument
1399 isShuffleExtractingFromLHS(ShuffleVectorInst &SVI, SmallVector<int, 16> &Mask) isShuffleExtractingFromLHS() argument
1514 Constant *Mask = Shuf.getMask(); canonicalizeInsertSplat() local
1608 Constant *Mask = Shuf.getMask(); foldSelectShuffle() local
1711 Constant *Mask; foldIdentityExtractShuffle() local
1748 SmallVector<int, 16> Mask = Shuf.getShuffleMask(); foldShuffleWithInsert() local
1871 SmallVector<int, 16> Mask = Shuf.getShuffleMask(); foldIdentityPaddedShuffles() local
1911 SmallVector<int, 16> Mask = SVI.getShuffleMask(); global() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
H A DCmpInstAnalysis.cpp68 Value *&X, APInt &Mask, bool LookThruTrunc) { in decomposeBitTestICmp()
82 Mask = APInt::getSignMask(C->getBitWidth()); in decomposeBitTestICmp()
89 Mask = APInt::getSignMask(C->getBitWidth()); in decomposeBitTestICmp()
96 Mask = APInt::getSignMask(C->getBitWidth()); in decomposeBitTestICmp()
103 Mask = APInt::getSignMask(C->getBitWidth()); in decomposeBitTestICmp()
110 Mask = -*C; in decomposeBitTestICmp()
117 Mask = ~*C; in decomposeBitTestICmp()
124 Mask = ~*C; in decomposeBitTestICmp()
131 Mask = -*C; in decomposeBitTestICmp()
137 Mask in decomposeBitTestICmp()
66 decomposeBitTestICmp(Value *LHS, Value *RHS, CmpInst::Predicate &Pred, Value *&X, APInt &Mask, bool LookThruTrunc) decomposeBitTestICmp() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/
H A DGPRArith.cpp351 ASSERT_EQ(((Value0)&Mask##Size) & ((Value1)&Mask##Size) ? ValueIfTrue \ in TEST_F()
369 Immediate((Imm)&Mask##Size)); \ in TEST_F()
381 ASSERT_EQ(((Value0)&Mask##Size) & ((Imm)&Mask##Size) ? ValueIfTrue \ in TEST_F()
411 ASSERT_EQ(((Value0)&Mask##Size) & ((Value1)&Mask##Size) ? ValueIfTrue \ in TEST_F()
428 Immediate((Value1)&Mask##Size)); \ in TEST_F()
439 ASSERT_EQ(((Value0)&Mask##Size) & ((Value1)&Mask##Siz in TEST_F()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/
H A DGPRArith.cpp382 ASSERT_EQ(((Value0)&Mask##Size) & ((Value1)&Mask##Size) ? ValueIfTrue \ in TEST_F()
399 Immediate((Imm)&Mask##Size)); \ in TEST_F()
409 ASSERT_EQ(((Value0)&Mask##Size) & ((Imm)&Mask##Size) ? ValueIfTrue \ in TEST_F()
437 ASSERT_EQ(((Value0)&Mask##Size) & ((Value1)&Mask##Size) ? ValueIfTrue \ in TEST_F()
454 Immediate((Value1)&Mask##Size)); \ in TEST_F()
465 ASSERT_EQ(((Value0)&Mask##Size) & ((Value1)&Mask##Siz in TEST_F()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp651 Index = 0x0FFFFFFF, // Mask of the index value.
763 ShuffleMask(ArrayRef<int> M) : Mask(M) {
764 for (unsigned I = 0, E = Mask.size(); I != E; ++I) {
765 int M = Mask[I];
773 ArrayRef<int> Mask;
777 size_t H = Mask.size()/2;
778 return ShuffleMask(Mask.take_front(H));
781 size_t H = Mask.size()/2;
782 return ShuffleMask(Mask.take_back(H));
787 for (int M : Mask)
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H A DRDFRegisters.h73 LaneBitmask Mask = LaneBitmask::getNone(); member
77 : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {} in RegisterRef()
80 return Reg != 0 && Mask.any(); in operator bool()
84 return Reg == RR.Reg && Mask == RR.Mask; in operator ==()
92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); in operator <()
124 return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); in getRefForUnit()
140 LaneBitmask Mask; member
231 PrintLaneMaskOpt(LaneBitmask M) : Mask(
232 LaneBitmask Mask; global() member
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H A DRDFRegisters.cpp56 UnitInfos[U].Mask = LaneBitmask::getAll(); in PhysicalRegisterInfo()
64 UI.Mask = P.second; in PhysicalRegisterInfo()
67 UI.Mask = RC->LaneMask; in PhysicalRegisterInfo()
69 UI.Mask = LaneBitmask::getAll(); in PhysicalRegisterInfo()
141 if (PA.second.any() && (PA.second & RA.Mask).none()) { in aliasRR()
147 if (PB.second.any() && (PB.second & RB.Mask).none()) { in aliasRR()
169 if (RR.Mask == LaneBitmask::getAll()) in aliasRM()
172 if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask) in aliasRM()
180 LaneBitmask M = RR.Mask; in aliasRM()
183 if ((SM & RR.Mask) in aliasRM()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/
H A DResourceManager.cpp51 void DefaultResourceStrategy::used(uint64_t Mask) { in used() argument
52 if (Mask > NextInSequenceMask) { in used()
53 RemovedFromNextInSequence |= Mask; in used()
57 NextInSequenceMask &= (~Mask); in used()
66 uint64_t Mask) in ResourceState()
67 : ProcResourceDescIndex(Index), ResourceMask(Mask), in ResourceState()
128 uint64_t Mask = ProcResID2Mask[I]; in ResourceManager() local
129 unsigned Index = getResourceStateIndex(Mask); in ResourceManager()
131 std::make_unique<ResourceState>(*SM.getProcResource(I), I, Mask); in ResourceManager()
136 uint64_t Mask in ResourceManager() local
65 ResourceState(const MCProcResourceDesc &Desc, unsigned Index, uint64_t Mask) ResourceState() argument
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/third_party/node/deps/v8/src/base/
H A Denum-set.h26 for (E e : init) bits |= Mask(e); in EnumSet()
32 return (bits_ & Mask(element)) != 0; in contains()
37 void Add(E element) { bits_ |= Mask(element); } in Add()
39 void Remove(E element) { bits_ &= ~Mask(element); } in Remove()
63 return EnumSet(bits_ | Mask(element)); in operator |()
66 return EnumSet(bits_ & Mask(element)); in operator &()
69 return EnumSet(bits_ & ~Mask(element)); in operator -()
81 static constexpr T Mask(E element) { in Mask() function in v8::base::EnumSet
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp127 const uint64_t Mask = 0xFFFF; in updateImm() local
131 Imm &= ~(Mask << (Idx * 16)); in updateImm()
134 Imm |= Mask << (Idx * 16); in updateImm()
155 const uint64_t Mask = 0xFFFF; in trySequenceOfOnes() local
178 uint64_t Inside = Mask; in trySequenceOfOnes()
211 OrrImm = updateImm(OrrImm, Idx, Inside != Mask); in trySequenceOfOnes()
249 const unsigned Mask = 0xFFFF; in expandMOVImmSimple() local
278 unsigned Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
294 Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
295 if (Imm16 == (isNeg ? Mask in expandMOVImmSimple()
307 const unsigned Mask = 0xFFFF; expandMOVImm() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/
H A DSmallBitVector.h277 // Mask off previous bits. in find_next()
292 // Mask in previous bits. in find_next_unset()
293 uintptr_t Mask = (uintptr_t(1) << Prev) - 1; in find_next_unset() local
294 Bits |= Mask; in find_next_unset()
391 uintptr_t Mask = EMask - IMask; in set() local
392 setSmallBits(getSmallBits() | Mask); in set()
422 uintptr_t Mask = EMask - IMask; in reset() local
423 setSmallBits(getSmallBits() & ~Mask); in reset()
629 /// Add '1' bits from Mask to this vector. Don't resize.
630 /// This computes "*this |= Mask"
631 setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) setBitsInMask() argument
640 clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) clearBitsInMask() argument
649 setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) setBitsNotInMask() argument
658 clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) clearBitsNotInMask() argument
667 applyMask(const uint32_t *Mask, unsigned MaskWords) applyMask() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/ADT/
H A DBitVector.h174 // Mask off previous bits. in find_next()
241 BitWord Mask = EMask - IMask; in set() local
242 Bits[I / BITWORD_SIZE] |= Mask; in set()
280 BitWord Mask = EMask - IMask; in reset() local
281 Bits[I / BITWORD_SIZE] &= ~Mask; in reset()
319 BitWord Mask = BitWord(1) << (Idx % BITWORD_SIZE);
320 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
481 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
482 /// This computes "*this |= Mask".
483 void setBitsInMask(const uint32_t *Mask, unsigne
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3770 SmallVector<int, 8> Mask;
3771 Mask.push_back(NumElems);
3773 Mask.push_back(i);
3774 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
4213 const uint32_t *Mask = RegInfo->getCallPreservedMask(
4215 assert(Mask && "Missing call preserved mask for calling convention");
4229 Mask = RegInfo->getNoPreservedMask();
4240 // Allocate a new Reg Mask and copy Mask.
4243 memcpy(RegMask, Mask, sizeo
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/third_party/vixl/src/aarch64/
H A Dinstructions-aarch64.h285 return (Mask(M) == V) ? 1 : 0; in IsMaskedValue()
302 Instr Mask(uint32_t mask) const { in Mask() function in vixl::aarch64::Instruction
423 return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask))); in GetSizeLS()
429 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask))); in GetSizeLSPair()
449 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed; in IsCondBranchImm()
453 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed; in IsUncondBranchImm()
457 return Mask(CompareBranchFMask) == CompareBranchFixed; in IsCompareBranch()
460 bool IsTestBranch() const { return Mask(TestBranchFMask) == TestBranchFixed; } in IsTestBranch()
465 return Mask(PCRelAddressingFMask) == PCRelAddressingFixed; in IsPCRelAddressing()
469 return Mask(LogicalImmediateFMas in IsLogicalImmediate()
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