| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 506 MTC1 = 4, enumerator
741 return Latency::MTC1; in Mthc1Latency()
749 return Latency::MTC1 + 1; in MoveLatency()
777 return Latency::MTC1 + Mthc1Latency() + Latency::CVT_D_L; in CvtDUwLatency()
779 return Latency::BRANCH + Latency::MTC1 + 1 + Latency::MTC1 + in CvtDUwLatency()
834 return 1 + Latency::MTC1 + Mthc1Latency() + Latency::BRANCH + Latency::SUB_D + in Trunc_uw_dLatency()
840 return 1 + Latency::MTC1 + Latency::BRANCH + Latency::SUB_S + in Trunc_uw_sLatency()
855 return Latency::MTC1; in FmoveLowLatency()
857 return Latency::MFHC1 + Latency::MTC1 in FmoveLowLatency()
[all...] |
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 535 MTC1 = 4, enumerator
830 return UlwLatency() + Latency::MTC1; in Ulwc1Latency()
1096 Latency::MFC1 + 1 + XorLatency() + Latency::MTC1; in NegsLatency()
1128 Latency::MTC1; in Float32RoundLatency()
1196 3 * Latency::DMFC1 + OrLatency() + Latency::MTC1 + Latency::MOV_S + in TruncUlSLatency()
1559 return Latency::MTC1 + Latency::CVT_D_W; in GetInstructionLatency()
1561 return Latency::MTC1 + Latency::CVT_S_W; in GetInstructionLatency()
1600 Latency::MTC1 + Latency::MFC1 + Latency::MTHC1 + 1; in GetInstructionLatency()
1605 Latency::MTC1 + 2 * Latency::MFC1 + 2 + MovzLatency(); in GetInstructionLatency()
1617 return Latency::MFHC1 + Latency::MTC1 in GetInstructionLatency()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 122 Opc = Mips::MTC1; in copyPhysReg()
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
815 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
|
| H A D | MipsInstructionSelector.cpp | 504 MachineInstrBuilder MTC1 = in select()
505 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
506 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
|
| H A D | MipsAsmPrinter.cpp | 879 // Because of the current td files for Mips32, the operands for MTC1 in EmitInstrRegReg()
883 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
|
| H A D | MipsRegisterBankInfo.cpp | 150 case Mips::MTC1: in isFloatingPointOpcodeDef()
|
| H A D | MipsCallLowering.cpp | 157 MIRBuilder.buildInstr(Mips::MTC1) in assignValueToReg()
|
| H A D | MipsFastISel.cpp | 397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
|
| H A D | MipsSEISelLowering.cpp | 3777 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
|
| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 243 #define MTC1 (HI(17) | (4 << 21)) macro
923 FAIL_IF(push_inst(compiler, MTC1 | TA(4 + arg_count) | FS(float_arg_count), MOVABLE_INS)); in sljit_emit_enter()
924 FAIL_IF(push_inst(compiler, MTC1 | TA(5 + arg_count) | FS(float_arg_count) | (1 << 11), MOVABLE_INS)); in sljit_emit_enter()
936 FAIL_IF(push_inst(compiler, MTC1 | TA(4 + arg_count) | FS(float_arg_count), MOVABLE_INS)); in sljit_emit_enter()
2595 FAIL_IF(push_inst(compiler, MTC1 | flags | T(src) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_conv_f64_from_sw()
2609 FAIL_IF(push_inst(compiler, MTC1 | flags | T(TMP_REG1) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_conv_f64_from_sw()
3633 FAIL_IF(push_inst(compiler, MTC1 | T(TMP_REG2) | FS(freg), MOVABLE_INS)); in sljit_emit_fmem()
3643 FAIL_IF(push_inst(compiler, MTC1 | T(TMP_REG2) | MEMF64_FS_FIRST(freg), MOVABLE_INS)); in sljit_emit_fmem()
3647 FAIL_IF(push_inst(compiler, MTC1 | T(TMP_REG2) | MEMF64_FS_SECOND(freg), MOVABLE_INS)); in sljit_emit_fmem()
3655 FAIL_IF(push_inst(compiler, MTC1 | ( in sljit_emit_fmem()
[all...] |
| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 644 MTC1 = ((0U << 3) + 4) << 21,
|
| H A D | assembler-mips64.cc | 2679 GenInstrRegister(COP1, MTC1, rt, fs, f0); in mtc1()
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 599 MTC1 = ((0U << 3) + 4) << 21,
|
| H A D | assembler-mips.cc | 2412 GenInstrRegister(COP1, MTC1, rt, fs, f0); in mtc1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3372 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3502 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3505 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3506 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
|
| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3651 case MTC1: in DecodeTypeRegisterCOP1()
|
| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3702 case MTC1: in DecodeTypeRegisterCOP1()
|