Searched refs:MSUB_D (Results 1 - 8 of 8) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 490 MSUB_D = 5, enumerator
725 return Latency::MSUB_D; in MsubDLatency()
|
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 520 MSUB_D = 5, enumerator
|
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 519 MSUB_D = 5, enumerator
|
| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 774 MSUB_D = ((5U << 3) + 1),
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 728 MSUB_D = ((5U << 3) + 1),
|
| H A D | assembler-mips.cc | 2577 GenInstrRegister(COP1X, fr, ft, fs, fd, MSUB_D); in msub_d()
|
| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3710 case MSUB_D: { in DecodeTypeRegisterCOP1X()
|
| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3771 case MSUB_D: { in DecodeTypeRegisterCOP1X()
|
Completed in 36 milliseconds