Searched refs:MOV_S (Results 1 - 12 of 12) sorted by relevance
| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_64.c | 186 ins = MOV_S | FMT_D | FS(float_arg_count) | FD(arg_count); in call_with_args()
188 ins = MOV_S | FMT_D | FS(SLJIT_FR0) | FD(TMP_FREG1); in call_with_args()
194 ins = MOV_S | FMT_S | FS(float_arg_count) | FD(arg_count); in call_with_args()
196 ins = MOV_S | FMT_S | FS(SLJIT_FR0) | FD(TMP_FREG1); in call_with_args()
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| H A D | sljitNativeMIPS_32.c | 154 ins = MOV_S | FMT_D | FS(SLJIT_FR0) | FD(TMP_FREG1); in call_with_args()
164 ins = MOV_S | FMT_S | FS(SLJIT_FR0) | FD(TMP_FREG1); in call_with_args()
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| H A D | sljitNativeMIPS_common.c | 242 #define MOV_S (HI(17) | FMT_S | LO(6)) macro
921 FAIL_IF(push_inst(compiler, MOV_S | FMT_D | FS(TMP_FREG1) | FD(SLJIT_FR0), MOVABLE_INS)); in sljit_emit_enter()
934 FAIL_IF(push_inst(compiler, MOV_S | FMT_S | FS(TMP_FREG1) | FD(SLJIT_FR0), MOVABLE_INS)); in sljit_emit_enter()
969 FAIL_IF(push_inst(compiler, MOV_S | FMT_D | FS(arg_count) | FD(float_arg_count), MOVABLE_INS)); in sljit_emit_enter()
971 FAIL_IF(push_inst(compiler, MOV_S | FMT_D | FS(TMP_FREG1) | FD(SLJIT_FR0), MOVABLE_INS)); in sljit_emit_enter()
976 FAIL_IF(push_inst(compiler, MOV_S | FMT_S | FS(arg_count) | FD(float_arg_count), MOVABLE_INS)); in sljit_emit_enter()
978 FAIL_IF(push_inst(compiler, MOV_S | FMT_S | FS(TMP_FREG1) | FD(SLJIT_FR0), MOVABLE_INS)); in sljit_emit_enter()
2708 FAIL_IF(push_inst(compiler, MOV_S | FMT(op) | FS(src) | FD(dst_r), MOVABLE_INS)); in sljit_emit_fop1()
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 503 MOV_S = 4, enumerator
978 return Latency::MOVF_FREG + 1 + Latency::BRANCH + Latency::MOV_S + 4 + in Float32RoundLatency()
987 Latency::MOVF_FREG + 1 + Latency::MOV_S; in Float32MaxLatency()
1001 Latency::MOVF_FREG + 1 + Latency::MOV_S; in Float32MinLatency()
1032 Latency::MOV_S + SltuLatency() + 4; in TruncUlSLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 502 MOV_S = 4, enumerator
1126 return Latency::MFC1 + 1 + Latency::BRANCH + Latency::MOV_S + 4 + in Float32RoundLatency()
1139 Latency::MFC1 + 1 + Latency::MOV_S; in Float32MaxLatency()
1161 Latency::MFC1 + 1 + Latency::MOV_S; in Float32MinLatency()
1196 3 * Latency::DMFC1 + OrLatency() + Latency::MTC1 + Latency::MOV_S + in TruncUlSLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 473 MOV_S = 4, enumerator
770 return Latency::MFC1 + ExtLatency() + Latency::BRANCH + Latency::MOV_S + 4 + in Float32RoundLatency()
1196 return Latency::MOV_S; // Estimated max. in Move_sLatency()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 662 MOV_S = ((0U << 3) + 6),
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| H A D | assembler-mips64.cc | 2896 GenInstrRegister(COP1, S, f0, fs, fd, MOV_S); in mov_s()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 616 MOV_S = ((0U << 3) + 6),
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| H A D | assembler-mips.cc | 2621 GenInstrRegister(COP1, S, f0, fs, fd, MOV_S); in mov_s()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 2773 case MOV_S: in DecodeTypeRegisterSRsType()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3253 case MOV_S: in DecodeTypeRegisterSRsType()
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