Home
last modified time | relevance | path

Searched refs:MIN3 (Results 1 - 25 of 26) sorted by relevance

12

/third_party/mesa3d/src/intel/common/
H A Dintel_guardband.h84 const float ss_ra_xmin = MIN3(x_min, m30 + m00, m30 - m00); in intel_calculate_guardband_size()
86 const float ss_ra_ymin = MIN3(y_min, m31 + m11, m31 - m11); in intel_calculate_guardband_size()
/third_party/mesa3d/src/asahi/lib/
H A Dtiling.h46 unsigned shift = util_logbase2_ceil(MIN3(width, height, 64)); in agx_select_tile_shift()
/third_party/mesa3d/src/util/
H A Du_math.h641 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C)) macro
644 #define MIN4( A, B, C, D ) ((A) < (B) ? MIN3(A, C, D) : MIN3(B, C, D))
H A Dmacros.h352 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C)) macro
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_setup_rect.c301 bbox.x0 = (MIN3(x0, x1, x2) + (FIXED_ONE-1)) >> FIXED_ORDER; in try_rect_cw()
303 bbox.y0 = (MIN3(y0, y1, y2) + (FIXED_ONE-1) + adj) >> FIXED_ORDER; in try_rect_cw()
H A Dlp_setup_tri.c307 bbox.x0 = MIN3(position->x[0], position->x[1], position->x[2]) >> FIXED_ORDER; in do_triangle_ccw()
311 bbox.y0 = (MIN3(position->y[0], position->y[1], position->y[2]) + adj) >> FIXED_ORDER; in do_triangle_ccw()
/third_party/mesa3d/src/glx/
H A Dindirect_glx.c387 gc->maxSmallRenderCommandSize = MIN3(bufSize, __GLX_RENDER_CMD_SIZE_LIMIT, in indirect_create_context_attribs()
/third_party/mesa3d/src/virtio/vulkan/
H A Dvn_instance.c108 instance_version = MIN3(instance_version, instance->renderer_api_version, in vn_instance_init_renderer_versions()
H A Dvn_physical_device.c699 uint32_t ver = MIN3(vk10_props->apiVersion, VN_MAX_API_VERSION, in vn_physical_device_init_properties()
1155 MIN3(props.apiVersion, instance->renderer_api_version, in vn_physical_device_init_renderer_version()
/third_party/mesa3d/src/panfrost/lib/
H A Dpan_blitter.c1513 unsigned minx = MAX2(MIN3(info->dst.start.x, info->dst.end.x, maxx), 0); in pan_blit_ctx_init()
1514 unsigned miny = MAX2(MIN3(info->dst.start.y, info->dst.end.y, maxy), 0); in pan_blit_ctx_init()
/third_party/mesa3d/src/gallium/frontends/nine/
H A Dnine_state.c2316 x2 = MIN3(x2, rect.x2, rt->desc.Width); in CSMT_ITEM_NO_WAIT()
2317 y2 = MIN3(y2, rect.y2, rt->desc.Height); in CSMT_ITEM_NO_WAIT()
2342 x2 = MIN3(x2, rect.x2, zsbuf_surf->desc.Width); in CSMT_ITEM_NO_WAIT()
2343 y2 = MIN3(y2, rect.y2, zsbuf_surf->desc.Height); in CSMT_ITEM_NO_WAIT()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs_scoreboard.cpp877 min_dist = MIN3(min_dist, dist, 7);
390 assert(from < n); if (is[from] != from) assign(is[from], to); is[from] = to; } } unsigned *is; unsigned n; }; struct dependency { dependency() : ordered(TGL_REGDIST_NULL), jp(), unordered(TGL_SBID_NULL), id(0), exec_all(false) {} dependency(tgl_regdist_mode mode, const ordered_address &jp, bool exec_all) : ordered(mode), jp(jp), unordered(TGL_SBID_NULL), id(0), exec_all(exec_all) {} dependency(tgl_sbid_mode mode, unsigned id, bool exec_all) : ordered(TGL_REGDIST_NULL), jp(), unordered(mode), id(id), exec_all(exec_all) {} tgl_regdist_mode ordered; ordered_address jp; tgl_sbid_mode unordered; unsigned id; bool exec_all; static const dependency done; friend bool operator==(const dependency &dep0, const dependency &dep1) { return dep0.ordered == dep1.ordered && dep0.jp == dep1.jp && dep0.unordered == dep1.unordered && dep0.id == dep1.id && dep0.exec_all == dep1.exec_all; } friend bool operator!=(const dependency &dep0, const dependency &dep1) { return !(dep0 == dep1); } }; const dependency dependency::done = dependency(TGL_REGDIST_DST, ordered_address(), false); bool is_valid(const dependency &dep) { return dep.ordered || dep.unordered; } dependency merge(equivalence_relation &eq, const dependency &dep0, const dependency &dep1) { dependency dep; if (dep0.ordered || dep1.ordered) { dep.ordered = dep0.ordered | dep1.ordered; for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) dep.jp.jp[p] = MAX2(dep0.jp.jp[p], dep1.jp.jp[p]); } if (dep0.unordered || dep1.unordered) { dep.unordered = dep0.unordered | dep1.unordered; dep.id = eq.link(dep0.unordered ? dep0.id : dep1.id, dep1.unordered ? dep1.id : dep0.id); } dep.exec_all = dep0.exec_all || dep1.exec_all; return dep; } dependency shadow(const dependency &dep0, const dependency &dep1) { if (dep0.ordered == TGL_REGDIST_SRC && is_valid(dep1) && !(dep1.unordered & TGL_SBID_DST) && !(dep1.ordered & TGL_REGDIST_DST)) { dependency dep = dep1; dep.ordered |= dep0.ordered; for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) dep.jp.jp[p] = MAX2(dep.jp.jp[p], dep0.jp.jp[p]); return dep; } else { return is_valid(dep1) ? dep1 : dep0; } } dependency transport(dependency dep, int delta[IDX(TGL_PIPE_ALL)]) { if (dep.ordered) { for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) { if (dep.jp.jp[p] > INT_MIN) dep.jp.jp[p] += delta[p]; } } return dep; } dependency dependency_for_read(dependency dep) { dep.ordered &= TGL_REGDIST_DST; return dep; } dependency dependency_for_write(const struct intel_device_info *devinfo, const fs_inst *inst, dependency dep) { if (!is_unordered(inst) && is_single_pipe(dep.jp, inferred_exec_pipe(devinfo, inst))) dep.ordered &= TGL_REGDIST_DST; return dep; } class scoreboard { public: dependency get(const fs_reg &r) const { if (const dependency *p = const_cast<scoreboard *>(this)->dep(r)) return *p; else return dependency(); } void set(const fs_reg &r, const dependency &d) { if (dependency *p = dep(r)) *p = d; } friend scoreboard merge(equivalence_relation &eq, const scoreboard &sb0, const scoreboard &sb1) { scoreboard sb; for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) sb.grf_deps[i] = merge(eq, sb0.grf_deps[i], sb1.grf_deps[i]); sb.addr_dep = merge(eq, sb0.addr_dep, sb1.addr_dep); sb.accum_dep = merge(eq, sb0.accum_dep, sb1.accum_dep); return sb; } friend scoreboard shadow(const scoreboard &sb0, const scoreboard &sb1) { scoreboard sb; for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) sb.grf_deps[i] = shadow(sb0.grf_deps[i], sb1.grf_deps[i]); sb.addr_dep = shadow(sb0.addr_dep, sb1.addr_dep); sb.accum_dep = shadow(sb0.accum_dep, sb1.accum_dep); return sb; } friend scoreboard transport(const scoreboard &sb0, int delta[IDX(TGL_PIPE_ALL)]) { scoreboard sb; for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) sb.grf_deps[i] = transport(sb0.grf_deps[i], delta); sb.addr_dep = transport(sb0.addr_dep, delta); sb.accum_dep = transport(sb0.accum_dep, delta); return sb; } friend bool operator==(const scoreboard &sb0, const scoreboard &sb1) { for (unsigned i = 0; i < ARRAY_SIZE(sb0.grf_deps); i++) { if (sb0.grf_deps[i] != sb1.grf_deps[i]) return false; } if (sb0.addr_dep != sb1.addr_dep) return false; if (sb0.accum_dep != sb1.accum_dep) return false; return true; } friend bool operator!=(const scoreboard &sb0, const scoreboard &sb1) { return !(sb0 == sb1); } private: dependency grf_deps[BRW_MAX_GRF]; dependency addr_dep; dependency accum_dep; dependency * dep(const fs_reg &r) { const unsigned reg = (r.file == VGRF ? r.nr + r.offset / REG_SIZE : reg_offset(r) / REG_SIZE); return (r.file == VGRF || r.file == FIXED_GRF ? &grf_deps[reg] : r.file == MRF ? &grf_deps[GFX7_MRF_HACK_START + reg] : r.file == ARF && reg >= BRW_ARF_ADDRESS && reg < BRW_ARF_ACCUMULATOR ? &addr_dep : r.file == ARF && reg >= BRW_ARF_ACCUMULATOR && reg < BRW_ARF_FLAG ? &accum_dep : NULL); } }; struct dependency_list { dependency_list() : deps(NULL), n(0) {} ~dependency_list() { free(deps); } void push_back(const dependency &dep) { deps = (dependency *)realloc(deps, (n + 1) * sizeof(*deps)); deps[n++] = dep; } unsigned size() const { return n; } const dependency & operator[](unsigned i) const { assert(i < n); return deps[i]; } dependency & operator[](unsigned i) { assert(i < n); return deps[i]; } private: dependency_list(const dependency_list &); dependency_list & operator=(const dependency_list &); dependency *deps; unsigned n; }; void add_dependency(const unsigned *ids, dependency_list &deps, dependency dep) { if (is_valid(dep)) { if (dep.unordered) dep.id = ids[dep.id]; for (unsigned i = 0; i < deps.size(); i++) { if (deps[i].exec_all != dep.exec_all && (!deps[i].exec_all || (dep.unordered & TGL_SBID_SET)) && (!dep.exec_all || (deps[i].unordered & TGL_SBID_SET))) continue; if (dep.ordered && deps[i].ordered) { for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) deps[i].jp.jp[p] = MAX2(deps[i].jp.jp[p], dep.jp.jp[p]); deps[i].ordered |= dep.ordered; deps[i].exec_all |= dep.exec_all; dep.ordered = TGL_REGDIST_NULL; } if (dep.unordered && deps[i].unordered && deps[i].id == dep.id) { deps[i].unordered |= dep.unordered; deps[i].exec_all |= dep.exec_all; dep.unordered = TGL_SBID_NULL; } } if (is_valid(dep)) deps.push_back(dep); } } tgl_swsb ordered_dependency_swsb(const dependency_list &deps, const ordered_address &jp, bool exec_all) { tgl_pipe p = TGL_PIPE_NONE; unsigned min_dist = ~0u; for (unsigned i = 0; i < deps.size(); i++) { if (deps[i].ordered && exec_all >= deps[i].exec_all) { for (unsigned q = 0; q < IDX(TGL_PIPE_ALL); q++) { const unsigned dist = jp.jp[q] - int64_t(deps[i].jp.jp[q]); const unsigned max_dist = (q == IDX(TGL_PIPE_LONG) ? 14 : 10); assert(jp.jp[q] > deps[i].jp.jp[q]); if (dist <= max_dist) { p = (p && IDX(p) != q ? TGL_PIPE_ALL : tgl_pipe(TGL_PIPE_FLOAT + q)); min_dist = MIN3(min_dist, dist, 7); } } } } return { p ? min_dist : 0, p }; } bool find_ordered_dependency(const dependency_list &deps, const ordered_address &jp, bool exec_all) { return ordered_dependency_swsb(deps, jp, exec_all).regdist; } tgl_sbid_mode find_unordered_dependency(const dependency_list &deps, tgl_sbid_mode unordered, bool exec_all) { if (unordered) { for (unsigned i = 0; i < deps.size(); i++) { if ((unordered & deps[i].unordered) && exec_all >= deps[i].exec_all) return deps[i].unordered; } } return TGL_SBID_NULL; } tgl_sbid_mode baked_unordered_dependency_mode(const struct intel_device_info *devinfo, const fs_inst *inst, const dependency_list &deps, const ordered_address &jp) { const bool exec_all = inst->force_writemask_all; const bool has_ordered = find_ordered_dependency(deps, jp, exec_all); const tgl_pipe ordered_pipe = ordered_dependency_swsb(deps, jp, exec_all).pipe; if (find_unordered_dependency(deps, TGL_SBID_SET, exec_all)) return find_unordered_dependency(deps, TGL_SBID_SET, exec_all); else if (has_ordered && is_unordered(inst)) return TGL_SBID_NULL; else if (find_unordered_dependency(deps, TGL_SBID_DST, exec_all) && (!has_ordered || ordered_pipe == inferred_sync_pipe(devinfo, inst))) return find_unordered_dependency(deps, TGL_SBID_DST, exec_all); else if (!has_ordered) return find_unordered_dependency(deps, TGL_SBID_SRC, exec_all); else return TGL_SBID_NULL; } bool baked_ordered_dependency_mode(const struct intel_device_info *devinfo, const fs_inst *inst, const dependency_list &deps, const ordered_address &jp) { const bool exec_all = inst->force_writemask_all; const bool has_ordered = find_ordered_dependency(deps, jp, exec_all); const tgl_pipe ordered_pipe = ordered_dependency_swsb(deps, jp, exec_all).pipe; const tgl_sbid_mode unordered_mode = baked_unordered_dependency_mode(devinfo, inst, deps, jp); if (!has_ordered) return false; else if (!unordered_mode) return true; else return ordered_pipe == inferred_sync_pipe(devinfo, inst) && unordered_mode == (is_unordered(inst) ? TGL_SBID_SET : TGL_SBID_DST); } void update_inst_scoreboard(const fs_visitor *shader, const ordered_address *jps, const fs_inst *inst, unsigned ip, scoreboard &sb) { const bool exec_all = inst->force_writemask_all; const struct intel_device_info *devinfo = shader->devinfo; const tgl_pipe p = inferred_exec_pipe(devinfo, inst); const ordered_address jp = p ? ordered_address(p, jps[ip].jp[IDX(p)]) : ordered_address(); const bool is_ordered = ordered_unit(devinfo, inst, IDX(TGL_PIPE_ALL)); for (unsigned i = 0; i < inst->sources; i++) { const dependency rd_dep = (inst->is_payload(i) || inst->is_math()) ? dependency(TGL_SBID_SRC, ip, exec_all) : is_ordered ? dependency(TGL_REGDIST_SRC, jp, exec_all) : dependency::done; for (unsigned j = 0; j < regs_read(inst, i); j++) { const fs_reg r = byte_offset(inst->src[i], REG_SIZE * j); sb.set(r, shadow(sb.get(r), rd_dep)); } } if (inst->reads_accumulator_implicitly()) sb.set(brw_acc_reg(8), dependency(TGL_REGDIST_SRC, jp, exec_all)); if (is_send(inst) && inst->base_mrf != -1) { const dependency rd_dep = dependency(TGL_SBID_SRC, ip, exec_all); for (unsigned j = 0; j < inst->mlen; j++) sb.set(brw_uvec_mrf(8, inst->base_mrf + j, 0), rd_dep); } const dependency wr_dep = is_unordered(inst) ? dependency(TGL_SBID_DST, ip, exec_all) : is_ordered ? dependency(TGL_REGDIST_DST, jp, exec_all) : dependency(); if (inst->writes_accumulator_implicitly(devinfo)) sb.set(brw_acc_reg(8), wr_dep); if (is_valid(wr_dep) && inst->dst.file != BAD_FILE && !inst->dst.is_null()) assign() argument
H A Dbrw_fs_generator.cpp103 const unsigned width = MIN3(reg_width, phys_width, max_hw_width); in brw_reg_from_fs_reg()
H A Dbrw_fs.cpp5090 return MIN3(devinfo->ver >= 8 ? 16 : 8,
/third_party/mesa3d/src/intel/tools/
H A Daubinator_viewer.cpp492 MIN3(window->len, in display_edit_window()
/third_party/mesa3d/src/gallium/drivers/lima/
H A Dlima_job.c97 fb->shift_min = MIN3(fb->shift_w, fb->shift_h, 2); in lima_get_fb_info()
/third_party/mesa3d/src/gallium/drivers/r300/
H A Dr300_state_derived.c830 level_count = MIN3(sampler->max_lod, in r300_merge_textures_and_samplers()
H A Dr300_emit.c1116 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count, in r300_emit_vs_state()
/third_party/mesa3d/src/gallium/drivers/zink/
H A Dzink_bo.c369 size = MIN3(bo->base.size / 16, in sparse_backing_alloc()
H A Dzink_screen.c979 return MIN3(get_smallest_buffer_heap(screen), in zink_get_shader_param()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
H A Dlvp_device.c207 return MIN3(min_vertex_pipeline_param(pscreen, param), in min_shader_param()
/third_party/mesa3d/src/mesa/main/
H A Dtexobj.c729 t->_MaxLevel = MIN3(t->Attrib.MaxLevel, in _mesa_test_texobj_completeness()
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_bo.c940 size = MIN3(bo->base.size / 16, in sparse_backing_alloc()
/third_party/mesa3d/src/compiler/glsl/
H A Dgl_nir_link_varyings.c589 output_size = MIN3(num_components, current_type_components_left, 4); in xfb_decl_store()
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_state.c5207 MIN3(isv->base.u.buf.size, isv->res->bo->size - isv->res->offset, in emit_sampler_view()
5248 MIN3(iv->base.u.buf.size, res->bo->size - res->offset - iv->base.u.buf.offset, in emit_image_view()

Completed in 66 milliseconds

12