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Searched refs:IsX (Results 1 - 11 of 11) sorted by relevance

/third_party/vixl/src/aarch64/
H A Doperands-aarch64.h600 return base_.IsX() && regoffset_.IsNone() && in IsScalarPlusImmediate()
607 return base_.IsX() && regoffset_.IsX() && in IsScalarPlusScalar()
616 return base_.IsX() && regoffset_.IsZRegister() && in IsScalarPlusVector()
627 return base_.IsZRegister() && regoffset_.IsX() && in IsVectorPlusScalar()
645 VIXL_ASSERT(base_.IsX()); in GetScalarBase()
H A Dassembler-sve-aarch64.cc468 VIXL_ASSERT(rdn.IsX()); \
476 V(uqdecb, (rdn.IsX() ? UQDECB_r_rs_x : UQDECB_r_rs_uw)) \
477 V(uqdech, (rdn.IsX() ? UQDECH_r_rs_x : UQDECH_r_rs_uw)) \
478 V(uqdecw, (rdn.IsX() ? UQDECW_r_rs_x : UQDECW_r_rs_uw)) \
479 V(uqdecd, (rdn.IsX() ? UQDECD_r_rs_x : UQDECD_r_rs_uw)) \
480 V(uqincb, (rdn.IsX() ? UQINCB_r_rs_x : UQINCB_r_rs_uw)) \
481 V(uqinch, (rdn.IsX() ? UQINCH_r_rs_x : UQINCH_r_rs_uw)) \
482 V(uqincw, (rdn.IsX() ? UQINCW_r_rs_x : UQINCW_r_rs_uw)) \
483 V(uqincd, (rdn.IsX() ? UQINCD_r_rs_x : UQINCD_r_rs_uw))
2029 VIXL_ASSERT(rdn.IsX()); in decp()
[all...]
H A Dmacro-assembler-sve-aarch64.cc252 VIXL_ASSERT(xd.IsX()); in Addvl()
253 VIXL_ASSERT(xn.IsX()); in Addvl()
309 VIXL_ASSERT(xd.IsX()); in CalculateSVEAddress()
H A Dregisters-aarch64.h337 bool IsX() const { return IsRegister() && Is64Bits(); }
H A Dassembler-aarch64.cc1149 VIXL_ASSERT(((emitop & LoadStorePairMask) != LDPSW_x) || rt.IsX()); in LoadStorePair()
3355 VIXL_ASSERT((index == 1) && vd.Is1D() && rn.IsX());
3363 VIXL_ASSERT((index == 1) && vn.Is1D() && rd.IsX());
5059 VIXL_ASSERT(vd.Is2D() == rn.IsX());
5132 VIXL_ASSERT(rn.IsX());
5172 VIXL_ASSERT(rd.IsX());
5209 VIXL_ASSERT(rd.IsX());
6823 return rt.IsX() ? LDR_x_lit : LDR_w_lit;
/third_party/node/deps/v8/src/diagnostics/arm64/
H A Ddisasm-arm64.cc3615 if (reg.IsX() && (reg.code() == 27)) { in AppendRegisterNameToOutput()
3617 } else if (reg.IsX() && (reg.code() == 29)) { in AppendRegisterNameToOutput()
3619 } else if (reg.IsX() && (reg.code() == 30)) { in AppendRegisterNameToOutput()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dregister-arm64.h158 bool IsX() const { return IsRegister() && Is64Bits(); } in IsX() function in v8::internal::CPURegister
H A Dassembler-arm64.cc1898 DCHECK(rn.IsX()); in ins()
1928 DCHECK(rd.IsX()); in smov()
2085 DCHECK(rd.IsX()); in umov()
2103 DCHECK_EQ(vd.Is2D(), rn.IsX()); in dup()
2655 DCHECK((index == 1) && vd.Is1D() && rn.IsX()); in fmov()
2661 DCHECK((index == 1) && vn.Is1D() && rd.IsX()); in fmov()
/third_party/node/deps/v8/src/baseline/arm64/
H A Dbaseline-assembler-arm64-inl.h528 DCHECK(lhs.IsX()); in AddSmi()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h707 bool IsX() const { return type_ == X_ARG; } in IsX() function in v8::internal::Simulator::CallArgument
H A Dsimulator-arm64.cc149 if (arg.IsX() && (index_x < 8)) { in CallImpl()
154 DCHECK(arg.IsD() || arg.IsX()); in CallImpl()

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