Searched refs:HasSVELane (Results 1 - 2 of 2) sorted by relevance
| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.h | 214 inline bool HasSVELane(T reg, int lane) const { in HasSVELane() function in vixl::aarch64::RegisterDump
221 VIXL_ASSERT(HasSVELane(reg, lane)); in GetSVELane()
415 if (!core->HasSVELane(reg, lane)) {
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| H A D | test-assembler-sve-aarch64.cc | 4524 if (!core.HasSVELane(zd_1, lane)) break;
6812 if (!core.HasSVELane(z26.VnB(), lane)) break;
6819 if (!core.HasSVELane(z27.VnH(), lane)) break;
6826 if (!core.HasSVELane(z28.VnS(), lane)) break;
6833 if (!core.HasSVELane(z29.VnD(), lane)) break;
12357 if (!core.HasSVELane(dn_result, lane)) break;
12367 if (!core.HasSVELane(dm_result, lane)) break;
12710 if (!core.HasSVELane(zd_asr, lane)) break;
12727 if (!core.HasSVELane(zd_lsr, lane)) break;
12735 if (!core.HasSVELane(zd_ls
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