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Searched refs:Halve (Results 1 - 4 of 4) sorted by relevance

/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc3383 add(vform, result, zdn, zm).Halve(vform); in Simulator()
3386 sub(vform, result, zdn, zm).Halve(vform); in Simulator()
3389 sub(vform, result, zm, zdn).Halve(vform); in Simulator()
3392 add(vform, result, zdn, zm).Halve(vform).Round(vform); in Simulator()
7586 add(vf, rd, rn, rm).Halve(vf); in Simulator()
7589 add(vf, rd, rn, rm).Halve(vf).Round(vf); in Simulator()
7595 sub(vf, rd, rn, rm).Halve(vf); in Simulator()
H A Dsimulator-aarch64.h967 LogicVRegister& Halve(VectorFormat vform) { in Halve() function in vixl::aarch64::LogicVRegister
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc4416 add(vf, rd, rn, rm).Halve(vf);
4419 add(vf, rd, rn, rm).Halve(vf).Round(vf);
4425 sub(vf, rd, rn, rm).Halve(vf);
H A Dsimulator-arm64.h618 LogicVRegister& Halve(VectorFormat vform) { in Halve() function in v8::internal::LogicVRegister

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