| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-fp-aarch64.cc | 4527 __ Fcvtzu(w0, s0);
4528 __ Fcvtzu(w1, s1);
4529 __ Fcvtzu(w2, s2);
4530 __ Fcvtzu(w3, s3);
4531 __ Fcvtzu(w4, s4);
4532 __ Fcvtzu(w5, s5);
4533 __ Fcvtzu(w6, s6);
4534 __ Fcvtzu(w7, s7);
4535 __ Fcvtzu(w8, d8);
4536 __ Fcvtzu(w
[all...] |
| H A D | test-disasm-neon-aarch64.cc | 3823 COMPARE_MACRO(Fcvtzu(v4.V2S(), v11.V2S()), in TEST()
3826 COMPARE_MACRO(Fcvtzu(v23.V4S(), v12.V4S()), in TEST()
3829 COMPARE_MACRO(Fcvtzu(v30.V2D(), v1.V2D()), in TEST()
3866 COMPARE_MACRO(Fcvtzu(s28, s29), "fcvtzu s28, s29"); in TEST()
3867 COMPARE_MACRO(Fcvtzu(d30, d31), "fcvtzu d30, d31"); in TEST()
3987 COMPARE_2REGMISC_FP16(Fcvtzu, "fcvtzu"); in TEST()
4446 COMPARE_MACRO(Fcvtzu(v3.V4H(), v1.V4H(), 5), "fcvtzu v3.4h, v1.4h, #5"); in TEST()
4447 COMPARE_MACRO(Fcvtzu(v4.V8H(), v2.V8H(), 6), "fcvtzu v4.8h, v2.8h, #6"); in TEST()
4448 COMPARE_MACRO(Fcvtzu(v5.V2S(), v3.V2S(), 11), "fcvtzu v5.2s, v3.2s, #11"); in TEST()
4449 COMPARE_MACRO(Fcvtzu(v in TEST()
[all...] |
| H A D | test-assembler-sve-aarch64.cc | 15497 &MacroAssembler::Fcvtzu,
15529 &MacroAssembler::Fcvtzu,
15561 &MacroAssembler::Fcvtzu,
15628 &MacroAssembler::Fcvtzu,
15671 &MacroAssembler::Fcvtzu,
15763 &MacroAssembler::Fcvtzu,
15818 &MacroAssembler::Fcvtzu,
|
| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1385 Fcvtzu(dst.gp().W(), src.fp().S()); // f32 -> i32 round to zero. in emit_type_conversion()
1414 Fcvtzu(dst.gp().W(), src.fp().D()); // f64 -> i32 round to zero. in emit_type_conversion()
1426 Fcvtzu(dst.gp().W(), src.fp().S()); in emit_type_conversion()
1432 Fcvtzu(dst.gp().W(), src.fp().D()); in emit_type_conversion()
1438 Fcvtzu(dst.gp().X(), src.fp().S()); in emit_type_conversion()
1444 Fcvtzu(dst.gp().X(), src.fp().D()); in emit_type_conversion()
1461 Fcvtzu(dst.gp().X(), src.fp().S()); // f32 -> i64 round to zero. in emit_type_conversion()
1477 Fcvtzu(dst.gp().X(), src.fp().D()); // f64 -> i64 round to zero. in emit_type_conversion()
2921 Fcvtzu(dst.fp().V4S(), src.fp().V4S()); in emit_i8x16_bitmask()
3043 Fcvtzu(ds in emit_i8x16_bitmask()
[all...] |
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1732 __ Fcvtzu(i.OutputRegister32(), i.InputFloat32Register(0)); in AssembleArchInstruction()
1743 __ Fcvtzu(i.OutputRegister32(), i.InputDoubleRegister(0)); in AssembleArchInstruction()
1777 __ Fcvtzu(i.OutputRegister64(), i.InputFloat32Register(0)); in AssembleArchInstruction()
1786 __ Fcvtzu(i.OutputRegister64(), i.InputDoubleRegister(0)); in AssembleArchInstruction()
2227 __ Fcvtzu(dst.V2D(), i.InputSimd128Register(0).V2D()); in AssembleArchInstruction()
2458 SIMD_UNOP_CASE(kArm64I32x4UConvertF32x4, Fcvtzu, 4S); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 1034 inline void Fcvtzu(const Register& rd, const VRegister& fn);
1035 void Fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Fcvtzu() function in v8::internal::TurboAssembler
|
| H A D | macro-assembler-arm64-inl.h | 604 void TurboAssembler::Fcvtzu(const Register& rd, const VRegister& fn) { in Fcvtzu() function in v8::internal::TurboAssembler
|
| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1617 void Fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) { in Fcvtzu() function in vixl::aarch64::MacroAssembler
3511 void Fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Fcvtzu() function in vixl::aarch64::MacroAssembler
4540 void Fcvtzu(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Fcvtzu() function in vixl::aarch64::MacroAssembler
|