| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-fp-aarch64.cc | 4321 __ Fcvtzs(w0, s0);
4322 __ Fcvtzs(w1, s1);
4323 __ Fcvtzs(w2, s2);
4324 __ Fcvtzs(w3, s3);
4325 __ Fcvtzs(w4, s4);
4326 __ Fcvtzs(w5, s5);
4327 __ Fcvtzs(w6, s6);
4328 __ Fcvtzs(w7, s7);
4329 __ Fcvtzs(w8, d8);
4330 __ Fcvtzs(w
[all...] |
| H A D | test-disasm-neon-aarch64.cc | 3814 COMPARE_MACRO(Fcvtzs(v4.V2S(), v11.V2S()), in TEST()
3817 COMPARE_MACRO(Fcvtzs(v23.V4S(), v12.V4S()), in TEST()
3820 COMPARE_MACRO(Fcvtzs(v30.V2D(), v1.V2D()), in TEST()
3864 COMPARE_MACRO(Fcvtzs(s24, s25), "fcvtzs s24, s25"); in TEST()
3865 COMPARE_MACRO(Fcvtzs(d26, d27), "fcvtzs d26, d27"); in TEST()
3986 COMPARE_2REGMISC_FP16(Fcvtzs, "fcvtzs"); in TEST()
4437 COMPARE_MACRO(Fcvtzs(v3.V4H(), v1.V4H(), 5), "fcvtzs v3.4h, v1.4h, #5"); in TEST()
4438 COMPARE_MACRO(Fcvtzs(v4.V8H(), v2.V8H(), 6), "fcvtzs v4.8h, v2.8h, #6"); in TEST()
4439 COMPARE_MACRO(Fcvtzs(v5.V2S(), v3.V2S(), 11), "fcvtzs v5.2s, v3.2s, #11"); in TEST()
4440 COMPARE_MACRO(Fcvtzs(v in TEST()
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| H A D | test-assembler-sve-aarch64.cc | 15489 &MacroAssembler::Fcvtzs,
15521 &MacroAssembler::Fcvtzs,
15553 &MacroAssembler::Fcvtzs,
15620 &MacroAssembler::Fcvtzs,
15663 &MacroAssembler::Fcvtzs,
15755 &MacroAssembler::Fcvtzs,
15810 &MacroAssembler::Fcvtzs,
|
| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1377 Fcvtzs(dst.gp().W(), src.fp().S()); // f32 -> i32 round to zero. in emit_type_conversion()
1399 Fcvtzs(dst.gp().W(), src.fp().D()); // f64 -> i32 round to zero. in emit_type_conversion()
1423 Fcvtzs(dst.gp().W(), src.fp().S()); in emit_type_conversion()
1429 Fcvtzs(dst.gp().W(), src.fp().D()); in emit_type_conversion()
1435 Fcvtzs(dst.gp().X(), src.fp().S()); in emit_type_conversion()
1441 Fcvtzs(dst.gp().X(), src.fp().D()); in emit_type_conversion()
1453 Fcvtzs(dst.gp().X(), src.fp().S()); // f32 -> i64 round to zero. in emit_type_conversion()
1469 Fcvtzs(dst.gp().X(), src.fp().D()); // f64 -> i64 round to zero. in emit_type_conversion()
2916 Fcvtzs(dst.fp().V4S(), src.fp().V4S()); in emit_i8x16_bitmask()
3037 Fcvtzs(ds in emit_i8x16_bitmask()
[all...] |
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1717 __ Fcvtzs(i.OutputRegister32(), i.InputFloat32Register(0)); in AssembleArchInstruction()
1729 __ Fcvtzs(i.OutputRegister32(), i.InputDoubleRegister(0)); in AssembleArchInstruction()
1746 __ Fcvtzs(i.OutputRegister64(), i.InputFloat32Register(0)); in AssembleArchInstruction()
1759 __ Fcvtzs(i.OutputRegister(0), i.InputDoubleRegister(0)); in AssembleArchInstruction()
2221 __ Fcvtzs(dst.V2D(), i.InputSimd128Register(0).V2D()); in AssembleArchInstruction()
2448 SIMD_UNOP_CASE(kArm64I32x4SConvertF32x4, Fcvtzs, 4S); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 1022 inline void Fcvtzs(const Register& rd, const VRegister& fn);
1023 void Fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Fcvtzs() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64-inl.h | 599 void TurboAssembler::Fcvtzs(const Register& rd, const VRegister& fn) { in Fcvtzs() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.cc | 2549 // Fcvtzs will saturate to INT64_MIN (0x800...00) or INT64_MAX (0x7FF...FF) in TryConvertDoubleToInt64()
2552 Fcvtzs(result.X(), double_input); in TryConvertDoubleToInt64()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1605 void Fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) { in Fcvtzs() function in vixl::aarch64::MacroAssembler
3506 void Fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Fcvtzs() function in vixl::aarch64::MacroAssembler
4535 void Fcvtzs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Fcvtzs() function in vixl::aarch64::MacroAssembler
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