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Searched refs:FSUB (Results 1 - 25 of 50) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qpu.h195 A_ALU2(FSUB)
H A Dvc4_qir.h675 QIR_ALU2(FSUB)
H A Dvc4_qpu_emit.c259 A(FSUB), in vc4_generate_code_block()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h295 FADD, FSUB, FMUL, FDIV, FREM, enumerator
H A DTargetLowering.h2285 case ISD::FSUB:
2528 /// Returns true if the FADD or FSUB node passed could legally be combined with
2532 assert(N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB); in isFMADLegalForFAddFSub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd in getArithmeticInstrCost()
544 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
697 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
757 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
758 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
840 { ISD::FSUB, MV in getArithmeticInstrCost()
[all...]
H A DX86IntrinsicsInfo.h922 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
923 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp378 case ISD::FSUB: in LegalizeOp()
878 case ISD::FSUB: in Expand()
1409 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1412 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB. in ExpandFNEG()
1413 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
H A DSelectionDAGBuilder.cpp3003 visitBinary(I, ISD::FSUB); in visitFSub()
4980 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
5117 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5134 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5140 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5159 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5165 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5171 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog()
5213 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5230 SDValue t3 = DAG.getNode(ISD::FSUB, d in expandLog2()
[all...]
H A DTargetLowering.cpp2548 case ISD::FSUB: in SimplifyDemandedVectorElts()
5534 if (LegalOperations && !isOperationLegalOrCustom(ISD::FSUB, VT)) in isNegatibleForFree()
5544 case ISD::FSUB: in isNegatibleForFree()
5637 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5643 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5648 case ISD::FSUB:
5656 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
6156 // TODO: Should any fast-math-flags be set for the FSUB?
6171 SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs);
6182 // TODO: Should any fast-math-flags be set for the FSUB
[all...]
H A DSelectionDAGDumper.cpp250 case ISD::FSUB: return "fsub"; in getOperationName()
H A DLegalizeFloatTypes.cpp121 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
1178 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
2135 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; in PromoteFloatResult()
H A DLegalizeDAG.cpp2415 Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
3159 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3160 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3252 case ISD::FSUB: {
4142 case ISD::FSUB:
4447 case ISD::FSUB:
/third_party/node/deps/v8/src/codegen/arm64/
H A Dconstants-arm64.h1223 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1224 FSUB_s = FSUB,
1225 FSUB_d = FSUB | FP64,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp405 case ISD::FSUB: in getArithmeticInstrCost()
H A DAMDGPUISelLowering.cpp276 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
425 setOperationAction(ISD::FSUB, VT, Expand); in AMDGPUTargetLowering()
498 setTargetDAGCombine(ISD::FSUB); in AMDGPUTargetLowering()
514 case ISD::FSUB: in fnegFoldsIntoOp()
2036 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); in LowerFREM()
2141 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2177 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND_LegalFTRUNC()
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativePPC_common.c182 #define FSUB (HI(63) | LO(20)) macro
2025 FAIL_IF(push_inst(compiler, FSUB | FD(dst_r) | FA(TMP_FREG1) | FB(TMP_FREG2))); in sljit_emit_fop1_conv_f64_from_sw()
2148 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FSUBS, FSUB) | FD(dst_r) | FA(src1) | FB(src2))); in sljit_emit_fop2()
H A DsljitNativeARM_64.c99 #define FSUB 0x1e603800 macro
1815 FAIL_IF(push_inst(compiler, (FSUB ^ inv_bits) | VD(dst_r) | VN(src1) | VM(src2))); in sljit_emit_fop2()
/third_party/vixl/src/aarch64/
H A Dconstants-aarch64.h1654 FSUB = FPDataProcessing2SourceFixed | 0x00003000, enumerator
1655 FSUB_h = FSUB | FP16,
1656 FSUB_s = FSUB,
1657 FSUB_d = FSUB | FP64,
/third_party/mesa3d/src/broadcom/compiler/
H A Dv3d_compiler.h1321 VIR_A_ALU2(FSUB)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1585 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering()
1622 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp133 setOperationAction(ISD::FSUB, MVT::f16, Promote); in MipsSETargetLowering()
396 setOperationAction(ISD::FSUB, Ty, Legal); in addMSAFloatType()
1925 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1712 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1737 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
3040 case ISD::FSUB: return LowerF128Op(Op, DAG, in LowerOperation()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1815 case ISD::FSUB: in SelectBinaryFPOp()
2857 return SelectBinaryFPOp(I, ISD::FSUB); in fastSelectInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp913 setOperationAction(ISD::FSUB, MVT::f128, Legal); in PPCTargetLowering()
971 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in PPCTargetLowering()
1022 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
7650 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC()
7660 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC()
7666 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC()
7672 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); in LowerSELECT_CC()
7678 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); in LowerSELECT_CC()
7812 // TODO: Are there fast-math-flags to propagate to this FSUB? in LowerFP_TO_INT()
7813 SDValue True = DAG.getNode(ISD::FSUB, d in LowerFP_TO_INT()
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