| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 1997 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1998 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1999 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
2000 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
2001 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
2002 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
2034 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
2035 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
2036 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
2037 { ISD::FSQRT, MV in getIntrinsicInstrCost()
[all...] |
| H A D | X86IntrinsicsInfo.h | 920 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
921 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| H A D | BasicTTIImpl.h | 397 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1220 ISDs.push_back(ISD::FSQRT); in getIntrinsicInstrCost()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 311 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
360 Opcode = ISD::FSQRT; break; in mightUseCTR()
|
| H A D | PPCISelLowering.cpp | 297 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
302 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
643 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
741 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
807 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1109 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
1112 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1115 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
1118 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
1185 setTargetDAGCombine(ISD::FSQRT); in PPCTargetLowering()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 193 case ISD::FSQRT: return "fsqrt"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 119 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1176 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2121 case ISD::FSQRT: in PromoteFloatResult()
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| H A D | LegalizeVectorOps.cpp | 419 case ISD::FSQRT: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 97 case ISD::FSQRT: in ScalarizeVectorResult()
891 case ISD::FSQRT: in SplitVectorResult()
2817 case ISD::FSQRT: in WidenVectorResult()
|
| H A D | DAGCombiner.cpp | 1576 case ISD::FSQRT: return visitFSQRT(N); in visit()
12775 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
12779 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
12787 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
12796 // it's still worthwhile to get rid of the FSQRT if possible. in visitFDIV()
12799 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
12802 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
12807 // We found a FSQRT, so try to make this fold: in visitFDIV()
12859 // FSQRT nodes have flags that propagate to the created nodes. in visitFSQRT()
12982 if (!DAG.getTargetLoweringInfo().isOperationLegalOrCustom(ISD::FSQRT, V in visitFPOW()
[all...] |
| H A D | LegalizeDAG.cpp | 3949 case ISD::FSQRT:
4508 case ISD::FSQRT:
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1715 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1740 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3046 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 151 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
395 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1921 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
|
| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 872 FSQRT = (3U << 17),
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 823 FSQRT = (3U << 17),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 207 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in WebAssemblyTargetLowering()
|
| /third_party/mesa3d/src/mesa/x86/ |
| H A D | assyntax.h | 767 #define FSQRT CHOICE(fsqrt, fsqrt, fsqrt) macro
1480 #define FSQRT fsqrt macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 1179 FSQRT = FSQRT_s,
|
| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 1171 FORMAT(FSQRT, "fsqrt"); in VisitFPDataProcessing1Source()
|
| /third_party/node/deps/v8/src/codegen/ppc/ |
| H A D | constants-ppc.h | 1949 V(fsqrt, FSQRT, 0xFC00002C) \
|
| H A D | assembler-ppc.cc | 1886 emit(EXT4 | FSQRT | frt.code() * B21 | frb.code() * B11 | rc); in fsqrt()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 271 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
446 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in AArch64TargetLowering()
481 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); in AArch64TargetLowering()
495 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); in AArch64TargetLowering()
722 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); in AArch64TargetLowering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 7569 if (RHS.getOpcode() == ISD::FSQRT) in lowerFastUnsafeFDIV()
8606 case ISD::FSQRT: in fp16SrcZerosHighBits()
8768 case ISD::FSQRT: in isCanonicalized()
|