| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | mdct_vfp.S | 247 fmrx OLDFPSCR, FPSCR
249 fmxr FPSCR, lr
260 fmxr FPSCR, OLDFPSCR
264 fmxr FPSCR, lr
273 fmxr FPSCR, OLDFPSCR
280 fmrx OLDFPSCR, FPSCR
282 fmxr FPSCR, lr
301 fmxr FPSCR, OLDFPSCR
308 fmxr FPSCR, lr
326 fmxr FPSCR, OLDFPSC
[all...] |
| H A D | fmtconvert_vfp.S | 46 fmrx a1, FPSCR
47 fmxr FPSCR, ip
125 fmxr FPSCR, a1
162 fmrx ip, FPSCR
163 fmxr FPSCR, lr
181 fmxr FPSCR, ip
199 fmrx ip, FPSCR
200 fmxr FPSCR, tmp
217 fmxr FPSCR, ip
|
| H A D | fft_vfp.S | 28 @ stored original FPSCR.
169 fmrx a2, FPSCR
170 fmxr FPSCR, a3
175 fmxr FPSCR, a2
326 fmrx a2, FPSCR
327 fmxr FPSCR, a3
332 fmxr FPSCR, a2
506 fmrx a2, FPSCR
507 fmxr FPSCR, a3
512 fmxr FPSCR, a
[all...] |
| H A D | synth_filter_vfp.S | 138 fmrx OLDFPSCR, FPSCR
140 fmxr FPSCR, lr
199 fmxr FPSCR, OLDFPSCR
|
| /third_party/ffmpeg/libavutil/arm/ |
| H A D | float_dsp_vfp.S | 89 fmrx OLDFPSCR, FPSCR
98 fmxr FPSCR, lr
171 fmxr FPSCR, lr
260 fmxr FPSCR, OLDFPSCR
355 fmrx OLDFPSCR, FPSCR
361 fmxr FPSCR, ip
406 fmxr FPSCR, ip
449 fmxr FPSCR, OLDFPSCR
|
| /third_party/ffmpeg/tests/checkasm/arm/ |
| H A D | checkasm.S | 43 .asciz "failed to preserve register FPSCR, changed bits: %x"
67 fmrx r4, FPSCR
135 fmrx r1, FPSCR
187 fmxr FPSCR, r2
|
| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-aarch32.cc | 141 __ Vmsr(FPSCR, r0); \
2818 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); in TEST() local
2821 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); in TEST() local
2824 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); in TEST() local
2849 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); in TEST() local
2852 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); in TEST() local
2855 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); in TEST() local
2880 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); in TEST() local
2883 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); in TEST() local
2886 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); in TEST() local
2911 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); TEST() local
2914 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); TEST() local
2917 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); TEST() local
2939 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); TEST() local
2943 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); TEST() local
2946 __ Vmrs(RegisterOrAPSR_nzcv(pc.GetCode()), FPSCR); TEST() local
[all...] |
| H A D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc | 1443 __ Vmsr(FPSCR, fpsr_bits); in TestHelper()
1454 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR); in TestHelper() local
|
| H A D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc | 1443 __ Vmsr(FPSCR, fpsr_bits); in TestHelper()
1454 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR); in TestHelper() local
|
| H A D | test-disasm-a32.cc | 3892 COMPARE_BOTH(Vmsr(FPSCR, r0), "vmsr FPSCR, r0\n"); in TEST()
3894 COMPARE_BOTH(Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR), in TEST()
3895 "vmrs r1, FPSCR\n"); in TEST()
3897 COMPARE_BOTH(Vmrs(RegisterOrAPSR_nzcv(pc.GetCode()), FPSCR), in TEST()
3898 "vmrs APSR_nzcv, FPSCR\n"); in TEST()
|
| /third_party/vixl/tools/test_generator/ |
| H A D | data_types.py | 521 class FPSCR(U32): class
528 __ Vmsr(FPSCR, fpsr_bits);
537 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR);
|
| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 1619 Format(instr, "vmsr'cond FPSCR, APSR"); in DecodeTypeVFP()
1621 Format(instr, "vmsr'cond FPSCR, 'rt"); in DecodeTypeVFP()
1625 Format(instr, "vmrs'cond APSR, FPSCR"); in DecodeTypeVFP()
1627 Format(instr, "vmrs'cond 'rt, FPSCR"); in DecodeTypeVFP()
|
| /third_party/vixl/src/aarch32/ |
| H A D | instructions-aarch32.cc | 365 case FPSCR: in GetName()
366 return "FPSCR"; in GetName()
|
| H A D | instructions-aarch32.h | 903 FPSCR = 0x1,
918 case FPSCR:
|
| H A D | macro-assembler-aarch32.cc | 513 Vmrs(RegisterOrAPSR_nzcv(tmp.GetCode()), FPSCR); in Printf() local
614 Vmsr(FPSCR, tmp); in Printf()
|
| /third_party/libunwind/libunwind/src/ptrace/ |
| H A D | _UPT_reg_offset.c | 470 [UNW_PPC32_FPSCR] = UNW_PPC_PT(FPSCR), \
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 195 markSuperRegs(Reserved, ARM::FPSCR); in getReservedRegs()
|
| H A D | ARMISelLowering.cpp | 5928 // The rounding mode is in bits 23:22 of the FPSCR. in LowerFLT_ROUNDS_()
5930 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) in LowerFLT_ROUNDS_()
5936 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops); in LowerFLT_ROUNDS_() local
5937 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
9267 // FIXME: Chain is not handled correctly here. Currently the FPSCR is implicit in LowerFSETCC()
|