| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 475 FP64 = 0x00400000
495 NEON_FP_2D = FP64 | NEON_Q
1120 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1123 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1126 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1128 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018
1137 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1140 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1150 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1160 FMOV_d_imm = FPImmediateFixed | FP64 |
[all...] |
| H A D | assembler-arm64-inl.h | 1057 Instr Assembler::FPType(VRegister fd) { return fd.Is64Bits() ? FP64 : FP32; } in FPType()
|
| H A D | assembler-arm64.h | 2242 return vd.Is64Bits() ? FP64 : FP32;
|
| /third_party/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 595 FP64 = 0x00400000 enumerator
617 NEON_FP_2D = FP64 | NEON_Q
1516 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1520 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1524 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1528 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1539 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1543 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1554 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1565 FMOV_d_imm = FPImmediateFixed | FP64 |
[all...] |
| H A D | simulator-aarch64.cc | 6335 case FP64: in Simulator()
6481 case FP64: in Simulator()
6644 if (instr->Mask(FP64) == FP64) { in Simulator()
9259 // from FP32/FP64 variations. in Simulator()
|
| H A D | assembler-aarch64.h | 7529 return FP64;
7606 return FP64;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.h | 117 bool FP64) const;
120 bool FP64) const;
|
| H A D | MipsSEFrameLowering.cpp | 85 MachineBasicBlock::iterator I, bool FP64) const;
87 MachineBasicBlock::iterator I, bool FP64) const;
288 bool FP64) const { in expandBuildPairF64()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
344 bool FP64) const { in expandExtractElementF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
|
| H A D | MipsSEInstrInfo.cpp | 770 bool FP64) const { in expandExtractElementF64()
784 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload in expandExtractElementF64()
802 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) in expandExtractElementF64()
803 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), in expandExtractElementF64()
812 bool isMicroMips, bool FP64) const {
838 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
858 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
859 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 48 WebAssembly::FP64}) in getReservedRegs()
138 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUSubtarget.h | 319 bool FP64; member in llvm::GCNSubtarget
480 return FP64; in hasFP64()
488 return FP64; in hasHWFP64()
1229 bool FP64; member in llvm::final
|
| H A D | AMDGPUSubtarget.cpp | 79 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be in initializeSubtargetDependencies()
121 // We don't support FP64 for EG/NI atm. in initializeSubtargetDependencies()
221 FP64(false),
542 FP64(false), in R600Subtarget()
|
| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/spirv_assembly/ |
| H A D | vktSpvAsmFloatControlsTests.cpp | 58 FP64 enumerator
1325 m_floatType = FP64; in TypeTestResults()
1701 mo[OID_CONV_FROM_FP64] = Op("conv_from_fp64", FLOAT_STORAGE_ONLY, false, FP64, "", convertSource, B_STATEMENT_USAGE_COMMANDS_TYPE_FLOAT); in init()
1713 = Op("sconst_conv_from_fp64", FLOAT_ARITHMETIC, true, FP64, in init()
1719 = Op("sconst_conv_from_fp64", FLOAT_ARITHMETIC, true, FP64, in init()
2093 // UnpackDouble2x32 is a special case as it operates only on FP64 and returns two ints, in init()
2234 bool isFP64 = typeTestResults->floatType() == FP64; in build()
2420 else // FP64 in build()
2906 m_typeData[FP64] = TypeData(); in TestGroupBuilderBase()
2907 m_typeData[FP64] in TestGroupBuilderBase()
[all...] |
| /third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/spirv_assembly/ |
| H A D | vktSpvAsmFloatControlsTests.cpp | 56 FP64 enumerator
1323 m_floatType = FP64; in TypeTestResults()
1699 mo[OID_CONV_FROM_FP64] = Op("conv_from_fp64", FLOAT_STORAGE_ONLY, false, FP64, "", convertSource, B_STATEMENT_USAGE_COMMANDS_TYPE_FLOAT); in init()
1711 = Op("sconst_conv_from_fp64", FLOAT_ARITHMETIC, true, FP64, in init()
1717 = Op("sconst_conv_from_fp64", FLOAT_ARITHMETIC, true, FP64, in init()
2091 // UnpackDouble2x32 is a special case as it operates only on FP64 and returns two ints, in init()
2232 bool isFP64 = typeTestResults->floatType() == FP64; in build()
2418 else // FP64 in build()
2904 m_typeData[FP64] = TypeData(); in TestGroupBuilderBase()
2905 m_typeData[FP64] in TestGroupBuilderBase()
[all...] |
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 3125 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS;
3216 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS;
3311 if (instr->Mask(FP64) == FP64) {
|