| /third_party/skia/src/core/ |
| H A D | SkCpu.h | 23 FMA = 1 << 8, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
92 // FMA doesn't fit neatly into this total ordering. in Supports()
94 // TODO: circle back on this if we find ourselves limited by lack of compile-time FMA in Supports()
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| H A D | SkCpu.cpp | 54 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; } in read_cpu_features()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUSubtarget.h | 320 bool FMA; member in llvm::GCNSubtarget
550 return FMA; in hasFMA()
1224 bool FMA; member in llvm::final
1309 bool hasFMA() const { return FMA; } in hasFMA()
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| H A D | SIISelLowering.cpp | 521 setOperationAction(ISD::FMA, MVT::f16, Legal); in SITargetLowering()
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal); in SITargetLowering()
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom); in SITargetLowering()
726 setTargetDAGCombine(ISD::FMA); in SITargetLowering()
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) && in isFPExtFoldable()
3884 // free fneg'd operands. As long as we have fast FMA (controlled by in enableAggressiveFMAFusion()
4087 case ISD::FMA: in LowerOperation()
7627 case ISD::FMA: in getFPTernOp()
7760 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, S in LowerFDIV32()
9757 SDValue FMA = N->getOperand(2); performFMACombine() local
[all...] |
| H A D | AMDGPUSubtarget.cpp | 537 FMA(false), in R600Subtarget()
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| H A D | AMDGPUISelDAGToDAG.cpp | 905 case ISD::FMA: in Select()
2104 bool IsFMA = N->getOpcode() == ISD::FMA; in SelectFMAD_FMA()
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| H A D | R600ISelLowering.cpp | 226 setOperationAction(ISD::FMA, MVT::f32, Expand); in R600TargetLowering()
227 setOperationAction(ISD::FMA, MVT::f64, Expand); in R600TargetLowering()
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| /third_party/mesa3d/src/panfrost/bifrost/test/ |
| H A D | test-scheduler-predicates.cpp | 57 TEST_F(SchedulerPredicates, FMA) in TEST_F()
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| /third_party/ffmpeg/libavcodec/x86/ |
| H A D | synth_filter.asm | 64 %else ; non-FMA
93 %else ; non-FMA
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| H A D | jpeg2000dsp.asm | 89 %else ; non FMA
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 355 /// FMA - Perform a * b + c with no intermediate rounding step.
356 FMA, enumerator
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| H A D | BasicTTIImpl.h | 1284 ISDs.push_back(ISD::FMA); in getIntrinsicInstrCost()
1287 ISDs.push_back(ISD::FMA); in getIntrinsicInstrCost()
1507 // If we can't lower fmuladd into an FMA estimate the cost as a floating in getIntrinsicInstrCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 3141 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); in UpgradeIntrinsicCall() local
3142 Rep = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3144 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3147 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3201 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3204 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3220 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
3222 Value *Odd = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3224 Value *Even = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3267 Function *FMA in UpgradeIntrinsicCall() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | InterleavedLoadCombinePass.cpp | 1184 auto FMA = MSSA.getMemoryAccess(First); in combine() local
1187 if (!MSSA.dominates(MADef, FMA)) in combine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 935 X86_INTRINSIC_DATA(avx512_vfmadd_f32, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
936 X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
937 X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
938 X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 256 case ISD::FMA: return "fma"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 95 case ISD::FMA: R = SoftenFloatRes_FMA(N); break; in SoftenFloatResult()
1157 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break; in ExpandFloatResult()
2137 case ISD::FMA: // FMA is same as FMAD in PromoteFloatResult()
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| H A D | DAGCombiner.cpp | 1573 case ISD::FMA: return visitFMA(N); in visit()
11512 /// Try to perform FMA combining on a given FADD node.
11527 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); in visitFADDForFMACombine()
11545 // Always prefer FMAD to FMA for precision. in visitFADDForFMACombine()
11546 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
11730 /// Try to perform FMA combining on a given FSUB node.
11744 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); in visitFSUBForFMACombine()
11763 // Always prefer FMAD to FMA for precision. in visitFSUBForFMACombine()
11764 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
12030 /// Try to perform FMA combinin
[all...] |
| /third_party/skia/third_party/externals/swiftshader/src/Pipeline/ |
| H A D | ShaderCore.hpp | 256 rr::RValue<sw::SIMD::Float> FMA(
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| /third_party/node/deps/v8/src/codegen/ia32/ |
| H A D | assembler-ia32.h | 1613 #define FMA(instr, length, prefix, escape1, escape2, extension, opcode) \ macro
1622 FMA_INSTRUCTION_LIST(FMA)
1623 #undef FMA macro
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| /third_party/node/deps/v8/src/codegen/x64/ |
| H A D | assembler-x64.h | 1376 #define FMA(instr, length, prefix, escape1, escape2, extension, opcode) \ macro
1385 FMA_INSTRUCTION_LIST(FMA)
1386 #undef FMA macro
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| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_from_tgsi.cpp | 748 NV50_IR_OPCODE_CASE(FMA, FMA); in translateOpcode()
848 NV50_IR_OPCODE_CASE(DFMA, FMA); in translateOpcode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1583 setOperationAction(ISD::FMA, MVT::f64, Expand); in HexagonTargetLowering()
1910 return isOperationLegalOrCustom(ISD::FMA, VT); in isFMAFasterThanFMulAndFAdd()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 137 setOperationAction(ISD::FMA, MVT::f16, Promote); in MipsSETargetLowering()
392 setOperationAction(ISD::FMA, Ty, Legal); in addMSAFloatType()
1903 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1620 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1625 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1630 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
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