Searched refs:DstMask (Results 1 - 5 of 5) sorted by relevance
/third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_dataflow.c | 469 unsigned int DstMask; member 626 unsigned int shared_mask = mask & d->DstMask; in get_readers_write_callback() 702 d->DstMask = dst_mask; in get_readers_for_single_write()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 1440 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx); in reMaterializeTrivialDef() local 1443 if ((SR.LaneMask & DstMask).none()) { in reMaterializeTrivialDef() 1602 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx); in eliminateUndefCopy() local 1604 if ((SR.LaneMask & DstMask).none()) in eliminateUndefCopy()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore() local 1208 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore() 1211 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
H A D | IceTargetLoweringMIPS32.cpp | 4637 auto *DstMask = makeReg(IceType_i32); in lowerIntrinsic() local 4649 _and(DstMask, T6, T5); in lowerIntrinsic() 4653 _or(RegAt, RegAt, DstMask); in lowerIntrinsic() 4657 Context.insert<InstFakeUse>(DstMask); in lowerIntrinsic()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1930 /// Does DstMask form a complementary pair with the mask provided by 1932 /// this asks whether DstMask zeroes precisely those bits that will be set by 1934 static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted, in isBitfieldDstMask() argument 1940 APInt SignificantDstMask = APInt(BitWidth, DstMask); in isBitfieldDstMask()
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