| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 414 DIVU = 50, enumerator
1138 return Latency::DIVU + Latency::MFLO; in DivuLatency()
1140 return Latency::DIVU; in DivuLatency()
1144 return 1 + Latency::DIVU + Latency::MFLO; in DivuLatency()
1146 return 1 + Latency::DIVU; in DivuLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 440 DIVU = 50, enumerator
652 return Latency::DIVU; in DivuLatency()
654 return Latency::DIVU + 1; in DivuLatency()
702 latency = Latency::DIVU + Latency::MFHI; in ModuLatency()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 189 #define DIVU (HI(0) | (2 << 6) | LO(27)) macro
198 #define DIVU (HI(0) | LO(27)) macro
2194 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1) | D(TMP_REG3), DR(TMP_REG3))); in sljit_emit_op0()
2202 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1) | D(TMP_REG3), DR(TMP_REG3))); in sljit_emit_op0()
2214 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); in sljit_emit_op0()
2218 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); in sljit_emit_op0()
|
| H A D | sljitNativeRISCV_common.c | 92 #define DIVU (F7(0x1) | F3(0x5) | OPC(0x33)) macro
1675 FAIL_IF(push_inst(compiler, DIVU | WORD | RD(SLJIT_R0) | RS1(SLJIT_R0) | RS2(SLJIT_R1))); in sljit_emit_op0()
1682 return push_inst(compiler, DIVU | WORD | RD(SLJIT_R0) | RS1(SLJIT_R0) | RS2(SLJIT_R1)); in sljit_emit_op0()
|
| /third_party/node/deps/openssl/openssl/crypto/bn/asm/ |
| H A D | mips.pl | 66 $DIVU="ddivu";
81 $DIVU="divu";
125 # define $DIVU(rs,rt) $DIVU $zero,rs,rt
957 $DIVU ($a0,$DH)
990 $DIVU ($a0,$DH)
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| /third_party/openssl/crypto/bn/asm/ |
| H A D | mips.pl | 66 $DIVU="ddivu";
81 $DIVU="divu";
125 # define $DIVU(rs,rt) $DIVU $zero,rs,rt
957 $DIVU ($a0,$DH)
990 $DIVU ($a0,$DH)
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 536 DIVU = ((3U << 3) + 3),
1345 FunctionFieldToBitNumber(DIVU) | FunctionFieldToBitNumber(DDIVU) |
|
| H A D | assembler-mips64.cc | 1803 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 533 DIVU = ((3U << 3) + 3),
1285 FunctionFieldToBitNumber(DIV) | FunctionFieldToBitNumber(DIVU) |
|
| H A D | assembler-mips.cc | 1844 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
|
| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 4017 case DIVU: in DecodeTypeRegisterSPECIAL()
|
| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3965 case DIVU: in DecodeTypeRegisterSPECIAL()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1411 case Mips::DIVU: in EmitInstrWithCustomInserter()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2065 case Mips::DIVU: in processInstruction()
|