Searched refs:DDIVU (Results 1 - 7 of 7) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 441 DDIVU = 50, enumerator
674 latency = Latency::DDIVU; in DdivuLatency()
676 latency = Latency::DDIVU + Latency::MFLO; in DdivuLatency()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 540 DDIVU = ((3U << 3) + 7),
1345 FunctionFieldToBitNumber(DIVU) | FunctionFieldToBitNumber(DDIVU) |
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| H A D | assembler-mips64.cc | 1847 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU); in ddivu()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 185 #define DDIVU (HI(0) | (2 << 6) | LO(31)) macro
196 #define DDIVU (HI(0) | LO(31)) macro
2198 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DDIVU : DDIV) | S(SLJIT_R0) | T(SLJIT_R1) | D(TMP_REG3), DR(TMP_REG3))); in sljit_emit_op0()
2216 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DDIVU : DDIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); in sljit_emit_op0()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 4048 case DDIVU: in DecodeTypeRegisterSPECIAL()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1428 case Mips::DDIVU: in EmitInstrWithCustomInserter()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2067 case Mips::DDIVU: in processInstruction()
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