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Searched refs:CpuFeature (Results 1 - 12 of 12) sorted by relevance

/third_party/node/deps/v8/src/codegen/
H A Dcpu-features.h15 enum CpuFeature { enum
110 static bool IsSupported(CpuFeature f) { in IsSupported()
114 static void SetSupported(CpuFeature f) { supported_ |= 1u << f; } in SetSupported()
115 static void SetUnsupported(CpuFeature f) { supported_ &= ~(1u << f); } in SetUnsupported()
H A Dassembler.h237 bool IsEnabled(CpuFeature f) { in IsEnabled()
240 void EnableCpuFeature(CpuFeature f) { in EnableCpuFeature()
455 CpuFeatureScope(AssemblerBase* assembler, CpuFeature f,
463 CpuFeatureScope(AssemblerBase* assembler, CpuFeature f, in CpuFeatureScope()
H A Dassembler.cc210 CpuFeatureScope::CpuFeatureScope(AssemblerBase* assembler, CpuFeature f, in CpuFeatureScope()
/third_party/node/deps/v8/src/codegen/shared-ia32-x64/
H A Dmacro-assembler-shared-ia32-x64.h101 base::Optional<CpuFeature> feature = base::nullopt;
191 AvxHelper<Dst, Arg, Args...>{this, base::Optional<CpuFeature>(SSE3)} \
199 AvxHelper<Dst, Arg, Args...>{this, base::Optional<CpuFeature>(SSSE3)} \
207 AvxHelper<Dst, Arg, Args...>{this, base::Optional<CpuFeature>(SSE4_1)} \
215 AvxHelper<Dst, Arg, Args...>{this, base::Optional<CpuFeature>(SSE4_2)} \
498 base::Optional<CpuFeature> feature = base::nullopt) { in PinsrHelper()
587 base::Optional<CpuFeature>(SSE4_1)); in Pinsrd()
/third_party/node/deps/v8/src/compiler/backend/
H A Dinstruction-selector.h380 explicit Features(CpuFeature f) : bits_(1u << f) {} in Features()
381 Features(CpuFeature f1, CpuFeature f2) : bits_((1u << f1) | (1u << f2)) {} in Features()
383 bool Contains(CpuFeature f) const { return (bits_ & (1u << f)); } in Contains()
389 bool IsSupported(CpuFeature feature) const { in IsSupported()
/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64.cc3709 CpuFeature feature) { in vinstr()
3720 CpuFeature feature) { in vinstr()
3731 LeadingOpcode m, VexW w, CpuFeature feature) { in vinstr()
3742 LeadingOpcode m, VexW w, CpuFeature feature);
3745 LeadingOpcode m, VexW w, CpuFeature feature);
3748 LeadingOpcode m, VexW w, CpuFeature feature);
3751 LeadingOpcode m, VexW w, CpuFeature feature);
3754 LeadingOpcode m, VexW w, CpuFeature feature);
H A Dassembler-x64.h935 SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature = AVX);
937 SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature = AVX);
941 LeadingOpcode m, VexW w, CpuFeature feature = AVX2);
2554 LeadingOpcode m, VexW w, CpuFeature feature);
2558 LeadingOpcode m, VexW w, CpuFeature feature);
2562 VexW w, CpuFeature feature);
2566 LeadingOpcode m, VexW w, CpuFeature feature);
2570 VexW w, CpuFeature feature);
/third_party/node/deps/v8/src/wasm/baseline/ia32/
H A Dliftoff-assembler-ia32.h2656 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) { in EmitSimdCommutativeBinOp()
2678 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) { in EmitSimdNonCommutativeBinOp()
2745 base::Optional<CpuFeature> feature = base::nullopt) { in EmitAllTrue()
3414 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1));
3428 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1));
3558 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1));
3572 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1));
3693 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1));
3700 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1));
3707 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_
[all...]
/third_party/node/deps/v8/src/wasm/baseline/x64/
H A Dliftoff-assembler-x64.h2289 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) { in EmitSimdCommutativeBinOp()
2311 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) { in EmitSimdNonCommutativeBinOp()
2373 base::Optional<CpuFeature> feature = base::nullopt) { in EmitAllTrue()
2989 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i8x16_min_s()
3003 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i8x16_max_s()
3133 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i16x8_min_u()
3147 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i16x8_max_u()
3267 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i32x4_mul()
3274 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i32x4_min_s()
3281 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_ in emit_i32x4_min_u()
[all...]
/third_party/node/deps/v8/src/codegen/ia32/
H A Dassembler-ia32.h1750 SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature = AVX);
1752 SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature = AVX);
1755 CpuFeature = AVX);
1758 CpuFeature = AVX);
H A Dassembler-ia32.cc3207 CpuFeature feature) { in vinstr()
3213 CpuFeature feature) { in vinstr()
3219 LeadingOpcode m, VexW w, CpuFeature feature) { in vinstr()
3229 CpuFeature feature) { in vinstr()
/third_party/node/deps/v8/src/codegen/mips/
H A Dconstants-mips.h102 return CpuFeatures::IsSupported(static_cast<CpuFeature>(check)); in IsMipsArchVariant()

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