Searched refs:CVT_S_L (Results 1 - 10 of 10) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 472 CVT_S_L = 4, enumerator
1367 return 1 + Latency::MOVT_DREG + Latency::CVT_S_L; in GetInstructionLatency()
1369 return Latency::MOVT_DREG + Latency::CVT_S_L; in GetInstructionLatency()
1379 2 * Latency::CVT_S_L + Latency::ADD_S; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 471 CVT_S_L = 4, enumerator
1563 return 1 + Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1565 return Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1575 2 * Latency::CVT_S_L + Latency::ADD_S; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 442 CVT_S_L = 4, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 722 CVT_S_L = ((4U << 3) + 0),
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| H A D | assembler-mips64.cc | 3055 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L); in cvt_s_l()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 677 CVT_S_L = ((4U << 3) + 0),
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| H A D | assembler-mips.cc | 2849 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L); in cvt_s_l()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3534 case CVT_S_L: in DecodeTypeRegisterLRsType()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3585 case CVT_S_L: in DecodeTypeRegisterLRsType()
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