Home
last modified time | relevance | path

Searched refs:CVT_D_L (Results 1 - 9 of 9) sorted by relevance

/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dinstruction-scheduler-riscv64.cc474 CVT_D_L = 4, enumerator
972 Latency::MOVF_HIGH_DREG + Latency::BRANCH + Latency::CVT_D_L + 2 + in Float64RoundLatency()
1371 return Latency::MOVT_DREG + Latency::CVT_D_L; in GetInstructionLatency()
1373 return 1 + Latency::MOVT_DREG + Latency::CVT_D_L; in GetInstructionLatency()
1376 2 * Latency::CVT_D_L + Latency::ADD_D; in GetInstructionLatency()
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dinstruction-scheduler-mips64.cc473 CVT_D_L = 4, enumerator
1116 Latency::DMFC1 + Latency::BRANCH + Latency::CVT_D_L + 2 + in Float64RoundLatency()
1567 return Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1569 return 1 + Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1572 2 * Latency::CVT_D_L + Latency::ADD_D; in GetInstructionLatency()
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dinstruction-scheduler-mips.cc444 CVT_D_L = 4, enumerator
761 4 + MoveLatency() + 1 + Latency::BRANCH + Latency::CVT_D_L; in Float64RoundLatency()
777 return Latency::MTC1 + Mthc1Latency() + Latency::CVT_D_L; in CvtDUwLatency()
/third_party/node/deps/v8/src/codegen/mips64/
H A Dconstants-mips64.h723 CVT_D_L = ((4U << 3) + 1),
H A Dassembler-mips64.cc3068 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L); in cvt_d_l()
/third_party/node/deps/v8/src/codegen/mips/
H A Dconstants-mips.h678 CVT_D_L = ((4U << 3) + 1),
H A Dassembler-mips.cc2863 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L); in cvt_d_l()
/third_party/node/deps/v8/src/execution/mips64/
H A Dsimulator-mips64.cc3530 case CVT_D_L: // Mips32r2 instruction. in DecodeTypeRegisterLRsType()
/third_party/node/deps/v8/src/execution/mips/
H A Dsimulator-mips.cc3573 case CVT_D_L: // Mips32r2 instruction. in DecodeTypeRegisterLRsType()

Completed in 43 milliseconds