| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 221 __ Bics(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-aarch32.cc | 997 __ Bics(r0, r1, r1); in TEST()
1009 __ Bics(r0, r0, Operand(r1, LSL, 4)); in TEST()
1021 __ Bics(r0, r0, Operand(r1, LSR, 4)); in TEST()
1033 __ Bics(r0, r0, Operand(r1, ASR, 4)); in TEST()
1045 __ Bics(r0, r0, Operand(r1, ROR, 1)); in TEST()
1059 __ Bics(r2, r0, Operand(r1, RRX)); in TEST()
1074 __ Bics(r2, r0, Operand(r1, RRX)); in TEST()
1085 __ Bics(r0, r0, 0xf000); in TEST()
1096 __ Bics(r0, r0, 0x7fffffff); in TEST()
3286 __ Bics(r in TEST()
[all...] |
| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 123 M(Bics) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 123 M(Bics) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 50 void MacroAssembler::Bics(const Register& rd, const Register& rn, in Bics() function in v8::internal::MacroAssembler
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| H A D | macro-assembler-arm64.h | 1534 inline void Bics(const Register& rd, const Register& rn,
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 830 void MacroAssembler::Bics(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.h | 794 void Bics(const Register& rd, const Register& rn, const Operand& operand);
3766 void Bics(const PRegisterWithLaneSize& pd, in Bics() function in vixl::aarch64::MacroAssembler
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1564 Bics(cond, rd, rn, operand); in MacroAssembler()
1571 Bics(cond, rd, rn, operand); in MacroAssembler()
1585 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1599 void Bics(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1600 Bics(al, rd, rn, operand); in MacroAssembler()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 834 __ Bics(w0, w1, Operand(w1)); in TEST()
846 __ Bics(w0, w0, Operand(w0, LSR, 1)); in TEST()
859 __ Bics(x0, x0, Operand(x1, ROR, 1)); in TEST()
871 __ Bics(x0, x0, 0x7fffffffffffffff); in TEST()
883 __ Bics(w0, w0, 0xfffffff0); in TEST()
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| H A D | test-assembler-sve-aarch64.cc | 1086 __ Bics(p1.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
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