Home
last modified time | relevance | path

Searched refs:BX (Results 1 - 21 of 21) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp100 {codeview::RegisterId::BX, X86::BX}, in initLLVMToSEHAndCVRegMapping()
621 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
670 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
671 return X86::BX; in getX86SubSuperRegisterOrZero()
706 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
742 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp692 uint16_t BX = im(2);
693 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
694 : RC[BX].is(1) ? BT::BitValue::Zero
701 uint16_t BX = im(2);
704 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
705 .fill(W1+(W1-BX), W0, Zero);
706 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
/third_party/ltp/tools/sparse/sparse-src/
H A Dcompile-i386.c204 AX, DX, CX, BX, SI, DI, BP, SP, // 16-bit enumerator
220 REGINFO( BL, "%bl", BX, EBX, ECX_EBX),
224 REGINFO( BH, "%bh", BX, EBX, ECX_EBX),
228 REGINFO( BX, "%bx", BL, BH, EBX, ECX_EBX),
236 REGINFO(EBX, "%ebx", BL, BH, BX, ECX_EBX),
242 REGINFO(ECX_EBX, "%ecx:%ebx", CL, CH, CX, ECX, BL, BH, BX, EBX),
251 REGSTORAGE(AX), REGSTORAGE(DX), REGSTORAGE(CX), REGSTORAGE(BX),
312 static struct regclass regclass_16 = { "16-bit", { AX, DX, CX, BX, SI, DI, BP }};
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h108 ENTRY(BX) \
122 ENTRY(BX) \
H A DX86Disassembler.cpp2105 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
2109 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
/third_party/node/deps/v8/src/codegen/ppc/
H A Dassembler-ppc.h460 int BX = 0, TX = 0; in xx2_form() local
463 BX = TX = 1; in xx2_form()
466 emit(instr | (t.code() & 0x1F) * B21 | (b.code() & 0x1F) * B11 | BX * B1 | in xx2_form()
493 int AX = 0, BX = 0, TX = 0; in xx3_form() local
496 AX = BX = TX = 1; in xx3_form()
500 (b.code() & 0x1F) * B11 | AX * B2 | BX * B1 | TX); in xx3_form()
H A Dassembler-ppc.cc425 case BX: in target_at()
455 *is_branch = (opcode == BX || opcode == BCX); in target_at_put()
459 case BX: { in target_at_put()
542 case BX: in max_reach_from()
723 emit(BX | (imm26 & kImm26Mask) | lk); in b()
H A Dconstants-ppc.h2249 V(b, BX, 0x48000000)
/third_party/lzma/Asm/x86/
H A D7zAsm.asm108 x3_W equ BX
/third_party/node/deps/v8/src/codegen/arm/
H A Dconstants-arm.h141 BX = 1 << 4, enumerator
H A Dassembler-arm.cc1516 emit(cond | B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BX | target.code()); in bx()
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeARM_32.c97 #define BX 0xe12fff10 macro
2301 return push_inst(compiler, BX | RM(TMP_REG2)); in sljit_emit_op_src()
2721 PTR_FAIL_IF(push_inst(compiler, (((type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)) & ~COND_MASK) | get_cc(compiler, type))); in sljit_emit_jump()
2939 PTR_FAIL_IF(push_inst(compiler, BX | RM(TMP_REG2))); in sljit_emit_call()
2977 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(src)); in sljit_emit_ijump()
2982 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)); in sljit_emit_ijump()
2999 FAIL_IF(push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1))); in sljit_emit_ijump()
3045 return push_inst(compiler, BX | RM(TMP_REG2)); in sljit_emit_icall()
H A DsljitNativeARM_T2_32.c119 #define BX 0x4700 macro
1899 return push_inst16(compiler, BX | RN3(TMP_REG2)); in sljit_emit_op_src()
2295 PTR_FAIL_IF(push_inst16(compiler, BX | RN3(TMP_REG1))); in sljit_emit_jump()
2513 PTR_FAIL_IF(push_inst16(compiler, BX | RN3(TMP_REG2))); in sljit_emit_call()
2552 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(src)); in sljit_emit_ijump()
2568 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(TMP_REG1)); in sljit_emit_ijump()
2611 return push_inst16(compiler, BX | RN3(TMP_REG2)); in sljit_emit_icall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h631 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
H A DARMAsmPrinter.cpp1321 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
2023 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
H A DARMFastISel.cpp1337 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; in SelectIndirectBr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1078 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed, in CheckBaseRegAndIndexRegAndScale()
1081 (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP && in CheckBaseRegAndIndexRegAndScale()
1114 if ((BaseReg != X86::BX && BaseReg != X86::BP) || in CheckBaseRegAndIndexRegAndScale()
2001 (IndexReg == X86::BX || IndexReg == X86::BP)) in ParseIntelOperand()
2921 "size, (R|E)BX will be used for the location"); in ParseInstruction()
/third_party/lz4/tests/
H A DMakefile418 $(LZ4) -BX $(FPREFIX)-hw -c -q | $(LZ4) -tv # test block checksum
/third_party/mesa3d/src/mesa/x86/
H A Dassyntax.h99 #define BX bx macro
161 #define BX %bx macro
824 #define W_BX BX
/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.cc2341 case BX: in DecodeType01()
/third_party/node/deps/v8/src/execution/ppc/
H A Dsimulator-ppc.cc1796 case BX: { in ExecuteGeneric()

Completed in 80 milliseconds