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Searched refs:BITFIELD_BIT (Results 1 - 25 of 116) sorted by relevance

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/third_party/mesa3d/src/imagination/vulkan/winsys/pvrsrvkm/
H A Dpvr_srv_bo.h43 #define PVR_SRV_MEMALLOCFLAG_CPU_CACHE_CLEAN BITFIELD_BIT(19U)
44 #define PVR_SRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE BITFIELD_BIT(14U)
45 #define PVR_SRV_MEMALLOCFLAG_ZERO_ON_ALLOC BITFIELD_BIT(31U)
46 #define PVR_SRV_MEMALLOCFLAG_SVM_ALLOC BITFIELD_BIT(17U)
47 #define PVR_SRV_MEMALLOCFLAG_POISON_ON_ALLOC BITFIELD_BIT(30U)
48 #define PVR_SRV_MEMALLOCFLAG_POISON_ON_FREE BITFIELD_BIT(29U)
49 #define PVR_SRV_MEMALLOCFLAG_GPU_READABLE BITFIELD_BIT(0U)
50 #define PVR_SRV_MEMALLOCFLAG_GPU_WRITEABLE BITFIELD_BIT(1U)
55 #define PVR_SRV_MEMALLOCFLAG_CPU_READABLE BITFIELD_BIT(4U)
56 #define PVR_SRV_MEMALLOCFLAG_CPU_WRITEABLE BITFIELD_BIT(
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H A Dpvr_srv_bridge.h114 #define PVR_TRANSFER_PREP_FLAGS_START BITFIELD_BIT(5U)
115 #define PVR_TRANSFER_PREP_FLAGS_END BITFIELD_BIT(6U)
121 #define SUPPORT_RGX_SET_OFFSET BITFIELD_BIT(4U)
122 #define DEBUG_SET_OFFSET BITFIELD_BIT(10U)
123 #define SUPPORT_BUFFER_SYNC_SET_OFFSET BITFIELD_BIT(11U)
124 #define OPTIONS_BIT31 BITFIELD_BIT(31U)
140 #define PVR_SRV_FLAGS_CLIENT_64BIT_COMPAT BITFIELD_BIT(5U)
146 #define PVR_BUFFER_FLAG_READ BITFIELD_BIT(0U)
147 #define PVR_BUFFER_FLAG_WRITE BITFIELD_BIT(1U)
715 #define RGX_CONTEXT_FLAG_DISABLESLR BITFIELD_BIT(
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/third_party/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_util.h72 FD_DBG_MSGS = BITFIELD_BIT(0),
73 FD_DBG_DISASM = BITFIELD_BIT(1),
74 FD_DBG_DCLEAR = BITFIELD_BIT(2),
75 FD_DBG_DDRAW = BITFIELD_BIT(3),
76 FD_DBG_NOSCIS = BITFIELD_BIT(4),
77 FD_DBG_DIRECT = BITFIELD_BIT(5),
78 FD_DBG_GMEM = BITFIELD_BIT(6),
79 FD_DBG_PERF = BITFIELD_BIT(7),
80 FD_DBG_NOBIN = BITFIELD_BIT(8),
81 FD_DBG_SYSMEM = BITFIELD_BIT(
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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_compiler.h255 IR3_DBG_SHADER_VS = BITFIELD_BIT(0),
256 IR3_DBG_SHADER_TCS = BITFIELD_BIT(1),
257 IR3_DBG_SHADER_TES = BITFIELD_BIT(2),
258 IR3_DBG_SHADER_GS = BITFIELD_BIT(3),
259 IR3_DBG_SHADER_FS = BITFIELD_BIT(4),
260 IR3_DBG_SHADER_CS = BITFIELD_BIT(5),
261 IR3_DBG_DISASM = BITFIELD_BIT(6),
262 IR3_DBG_OPTMSGS = BITFIELD_BIT(7),
263 IR3_DBG_FORCES2EN = BITFIELD_BIT(8),
264 IR3_DBG_NOUBOOPT = BITFIELD_BIT(
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/third_party/mesa3d/src/intel/ds/
H A Dintel_driver_ds.h45 INTEL_DS_DEPTH_CACHE_FLUSH_BIT = BITFIELD_BIT(0),
46 INTEL_DS_DATA_CACHE_FLUSH_BIT = BITFIELD_BIT(1),
47 INTEL_DS_HDC_PIPELINE_FLUSH_BIT = BITFIELD_BIT(2),
48 INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT = BITFIELD_BIT(3),
49 INTEL_DS_TILE_CACHE_FLUSH_BIT = BITFIELD_BIT(4),
50 INTEL_DS_STATE_CACHE_INVALIDATE_BIT = BITFIELD_BIT(5),
51 INTEL_DS_CONST_CACHE_INVALIDATE_BIT = BITFIELD_BIT(6),
52 INTEL_DS_VF_CACHE_INVALIDATE_BIT = BITFIELD_BIT(7),
53 INTEL_DS_TEXTURE_CACHE_INVALIDATE_BIT = BITFIELD_BIT(8),
54 INTEL_DS_INST_CACHE_INVALIDATE_BIT = BITFIELD_BIT(
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/third_party/mesa3d/src/gallium/drivers/panfrost/
H A Dpan_context.h63 PAN_DIRTY_VIEWPORT = BITFIELD_BIT(0),
64 PAN_DIRTY_SCISSOR = BITFIELD_BIT(1),
65 PAN_DIRTY_VERTEX = BITFIELD_BIT(2),
66 PAN_DIRTY_PARAMS = BITFIELD_BIT(3),
67 PAN_DIRTY_DRAWID = BITFIELD_BIT(4),
68 PAN_DIRTY_TLS_SIZE = BITFIELD_BIT(5),
69 PAN_DIRTY_ZS = BITFIELD_BIT(6),
70 PAN_DIRTY_BLEND = BITFIELD_BIT(7),
71 PAN_DIRTY_MSAA = BITFIELD_BIT(8),
72 PAN_DIRTY_OQ = BITFIELD_BIT(
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/third_party/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_screen.h59 SP_DBG_VS = BITFIELD_BIT(0),
60 /* SP_DBG_TCS = BITFIELD_BIT(1), */
61 /* SP_DBG_TES = BITFIELD_BIT(2), */
62 SP_DBG_GS = BITFIELD_BIT(3),
63 SP_DBG_FS = BITFIELD_BIT(4),
64 SP_DBG_CS = BITFIELD_BIT(5),
65 SP_DBG_USE_LLVM = BITFIELD_BIT(6),
66 SP_DBG_NO_RAST = BITFIELD_BIT(7),
67 SP_DBG_USE_TGSI = BITFIELD_BIT(8),
/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_debug.h37 #define DEBUG_MESA BITFIELD_BIT(0)
38 #define DEBUG_PRINT_IR BITFIELD_BIT(1)
39 #define DEBUG_FALLBACK BITFIELD_BIT(2)
40 #define DEBUG_BUFFER BITFIELD_BIT(3)
41 #define DEBUG_WIREFRAME BITFIELD_BIT(4)
42 #define DEBUG_GREMEDY BITFIELD_BIT(5)
43 #define DEBUG_NOREADPIXCACHE BITFIELD_BIT(6)
/third_party/mesa3d/src/imagination/vulkan/winsys/
H A Dpvr_winsys.h99 #define PVR_WINSYS_BO_FLAG_CPU_ACCESS BITFIELD_BIT(0U)
105 #define PVR_WINSYS_BO_FLAG_GPU_UNCACHED BITFIELD_BIT(1U)
111 #define PVR_WINSYS_BO_FLAG_PM_FW_PROTECT BITFIELD_BIT(2U)
116 #define PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC BITFIELD_BIT(3U)
248 #define PVR_WINSYS_TRANSFER_FLAG_START BITFIELD_BIT(0U)
249 #define PVR_WINSYS_TRANSFER_FLAG_END BITFIELD_BIT(1U)
296 #define PVR_WINSYS_COMPUTE_FLAG_PREVENT_ALL_OVERLAP BITFIELD_BIT(0U)
297 #define PVR_WINSYS_COMPUTE_FLAG_SINGLE_CORE BITFIELD_BIT(1U)
322 #define PVR_WINSYS_JOB_BO_FLAG_WRITE BITFIELD_BIT(0U)
330 #define PVR_WINSYS_GEOM_FLAG_FIRST_GEOMETRY BITFIELD_BIT(
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/third_party/mesa3d/src/panfrost/lib/tests/
H A Dtest-earlyzs.cpp37 #define ZS_WRITEMASK BITFIELD_BIT(0)
38 #define ALPHA2COV BITFIELD_BIT(1)
39 #define ZS_ALWAYS_PASSES BITFIELD_BIT(2)
40 #define DISCARD BITFIELD_BIT(3)
41 #define WRITES_Z BITFIELD_BIT(4)
42 #define WRITES_S BITFIELD_BIT(5)
43 #define WRITES_COV BITFIELD_BIT(6)
44 #define SIDEFX BITFIELD_BIT(7)
45 #define API_EARLY BITFIELD_BIT(8)
/third_party/mesa3d/src/compiler/
H A Dshader_enums.h243 #define VERT_BIT_POS BITFIELD_BIT(VERT_ATTRIB_POS)
244 #define VERT_BIT_NORMAL BITFIELD_BIT(VERT_ATTRIB_NORMAL)
245 #define VERT_BIT_COLOR0 BITFIELD_BIT(VERT_ATTRIB_COLOR0)
246 #define VERT_BIT_COLOR1 BITFIELD_BIT(VERT_ATTRIB_COLOR1)
247 #define VERT_BIT_FOG BITFIELD_BIT(VERT_ATTRIB_FOG)
248 #define VERT_BIT_COLOR_INDEX BITFIELD_BIT(VERT_ATTRIB_COLOR_INDEX)
249 #define VERT_BIT_TEX0 BITFIELD_BIT(VERT_ATTRIB_TEX0)
250 #define VERT_BIT_TEX1 BITFIELD_BIT(VERT_ATTRIB_TEX1)
251 #define VERT_BIT_TEX2 BITFIELD_BIT(VERT_ATTRIB_TEX2)
252 #define VERT_BIT_TEX3 BITFIELD_BIT(VERT_ATTRIB_TEX
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/third_party/mesa3d/src/imagination/vulkan/
H A Dpvr_bo.h57 #define PVR_BO_ALLOC_FLAG_CPU_ACCESS BITFIELD_BIT(0U)
63 (BITFIELD_BIT(1U) | PVR_BO_ALLOC_FLAG_CPU_ACCESS)
68 #define PVR_BO_ALLOC_FLAG_GPU_UNCACHED BITFIELD_BIT(2U)
74 #define PVR_BO_ALLOC_FLAG_PM_FW_PROTECT BITFIELD_BIT(3U)
79 #define PVR_BO_ALLOC_FLAG_ZERO_ON_ALLOC BITFIELD_BIT(4U)
H A Dpvr_tex_state.h38 #define PVR_TEXFLAGS_INDEX_LOOKUP BITFIELD_BIT(0U)
41 #define PVR_TEXFLAGS_BORDER BITFIELD_BIT(1U)
47 #define PVR_TEXFLAGS_BUFFER BITFIELD_BIT(2U)
H A Dpvr_private.h137 PVR_PIPELINE_STAGE_GEOM_BIT = BITFIELD_BIT(PVR_JOB_TYPE_GEOM),
138 PVR_PIPELINE_STAGE_FRAG_BIT = BITFIELD_BIT(PVR_JOB_TYPE_FRAG),
139 PVR_PIPELINE_STAGE_COMPUTE_BIT = BITFIELD_BIT(PVR_JOB_TYPE_COMPUTE),
140 PVR_PIPELINE_STAGE_TRANSFER_BIT = BITFIELD_BIT(PVR_JOB_TYPE_TRANSFER),
734 #define PVR_DYNAMIC_STATE_BIT_VIEWPORT BITFIELD_BIT(0U)
735 #define PVR_DYNAMIC_STATE_BIT_SCISSOR BITFIELD_BIT(1U)
736 #define PVR_DYNAMIC_STATE_BIT_LINE_WIDTH BITFIELD_BIT(2U)
737 #define PVR_DYNAMIC_STATE_BIT_DEPTH_BIAS BITFIELD_BIT(3U)
738 #define PVR_DYNAMIC_STATE_BIT_STENCIL_COMPARE_MASK BITFIELD_BIT(4U)
739 #define PVR_DYNAMIC_STATE_BIT_STENCIL_WRITE_MASK BITFIELD_BIT(
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H A Dpvr_hardcode.c231 assert(data->graphics.flags & BITFIELD_BIT(stage)); in pvr_hard_code_graphics_shader()
261 assert(data->graphics.flags & BITFIELD_BIT(MESA_SHADER_VERTEX)); in pvr_hard_code_graphics_vertex_state()
276 assert(data->graphics.flags & BITFIELD_BIT(MESA_SHADER_FRAGMENT)); in pvr_hard_code_graphics_fragment_state()
294 assert(data->graphics.flags & BITFIELD_BIT(stage)); in pvr_hard_code_graphics_get_build_info()
/third_party/mesa3d/src/imagination/rogue/
H A Drogue_operand.h142 ROGUE_REG_ACCESS_READ = BITFIELD_BIT(0U), /** Read-only. */
143 ROGUE_REG_ACCESS_WRITE = BITFIELD_BIT(1U), /* Write-only. */
153 ROGUE_REG_MOD_IDX = BITFIELD_BIT(0U), /** Index modifier. */
154 ROGUE_REG_MOD_DIM = BITFIELD_BIT(1U), /** Dimension modifier. */
/third_party/mesa3d/src/gallium/drivers/v3d/
H A Dv3d_screen.c917 screen->prim_types = BITFIELD_BIT(PIPE_PRIM_POINTS) | in v3d_screen_create()
918 BITFIELD_BIT(PIPE_PRIM_LINES) | in v3d_screen_create()
919 BITFIELD_BIT(PIPE_PRIM_LINE_LOOP) | in v3d_screen_create()
920 BITFIELD_BIT(PIPE_PRIM_LINE_STRIP) | in v3d_screen_create()
921 BITFIELD_BIT(PIPE_PRIM_TRIANGLES) | in v3d_screen_create()
922 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_STRIP) | in v3d_screen_create()
923 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_FAN) | in v3d_screen_create()
924 BITFIELD_BIT(PIPE_PRIM_LINES_ADJACENCY) | in v3d_screen_create()
925 BITFIELD_BIT(PIPE_PRIM_LINE_STRIP_ADJACENCY) | in v3d_screen_create()
926 BITFIELD_BIT(PIPE_PRIM_TRIANGLES_ADJACENC in v3d_screen_create()
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/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_screen.c612 screen->prim_types = BITFIELD_BIT(PIPE_PRIM_POINTS) | in vc4_screen_create()
613 BITFIELD_BIT(PIPE_PRIM_LINES) | in vc4_screen_create()
614 BITFIELD_BIT(PIPE_PRIM_LINE_LOOP) | in vc4_screen_create()
615 BITFIELD_BIT(PIPE_PRIM_LINE_STRIP) | in vc4_screen_create()
616 BITFIELD_BIT(PIPE_PRIM_TRIANGLES) | in vc4_screen_create()
617 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_STRIP) | in vc4_screen_create()
618 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_FAN); in vc4_screen_create()
/third_party/mesa3d/src/asahi/lib/
H A Dagx_device.h37 AGX_DBG_TRACE = BITFIELD_BIT(0),
38 AGX_DBG_DEQP = BITFIELD_BIT(1),
39 AGX_DBG_NO16 = BITFIELD_BIT(2),
/third_party/mesa3d/src/panfrost/bifrost/valhall/
H A Dva_insert_flow.c147 st->memory |= BITFIELD_BIT(I->slot); in bi_push_instr()
150 st->varying |= BITFIELD_BIT(I->slot); in bi_push_instr()
157 st->varying &= ~BITFIELD_BIT(slot); in bi_pop_slot()
158 st->memory &= ~BITFIELD_BIT(slot); in bi_pop_slot()
160 return BITFIELD_BIT(slot); in bi_pop_slot()
223 if (st->write[i] || ((st->varying | st->memory) & BITFIELD_BIT(i))) in bi_set_dependencies()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_nir.c148 if (nir->options->support_indirect_inputs & BITFIELD_BIT(nir->info.stage) || in si_nir_late_opts()
149 nir->options->support_indirect_outputs & BITFIELD_BIT(nir->info.stage)) in si_nir_late_opts()
179 ~(BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE) | BITFIELD_BIT(GLSL_SAMPLER_DIM_BUF)), in si_late_optimize_16bit_samplers()
186 .sampler_dims = ~BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE), in si_late_optimize_16bit_samplers()
H A Dsi_clear.c332 bool bit = value.ub[i / 8] & BITFIELD_BIT(i % 8); in gfx11_get_dcc_clear_parameters()
944 zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level); in si_fast_clear()
945 zstex->depth_cleared_level_mask |= BITFIELD_BIT(level); in si_fast_clear()
954 zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level); in si_fast_clear()
955 zstex->depth_cleared_level_mask |= BITFIELD_BIT(level); in si_fast_clear()
956 zstex->stencil_cleared_level_mask_once |= BITFIELD_BIT(level); in si_fast_clear()
1021 zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level); in si_fast_clear()
1022 zstex->depth_cleared_level_mask |= BITFIELD_BIT(level); in si_fast_clear()
1035 zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level); in si_fast_clear()
1036 zstex->depth_cleared_level_mask |= BITFIELD_BIT(leve in si_fast_clear()
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/third_party/mesa3d/src/imagination/vulkan/pds/
H A Dpvr_pds.h920 #define PVR_PDS_VERTEX_FLAGS_VERTEX_ID_REQUIRED BITFIELD_BIT(0U)
921 #define PVR_PDS_VERTEX_FLAGS_INSTANCE_ID_REQUIRED BITFIELD_BIT(1U)
922 #define PVR_PDS_VERTEX_FLAGS_DRAW_INDIRECT_VARIANT BITFIELD_BIT(2U)
923 #define PVR_PDS_VERTEX_FLAGS_BASE_INSTANCE_VARIANT BITFIELD_BIT(3U)
924 #define PVR_PDS_VERTEX_FLAGS_BASE_INSTANCE_REQUIRED BITFIELD_BIT(4U)
927 #define PVR_PDS_VERTEX_FLAGS_BASE_VERTEX_REQUIRED BITFIELD_BIT(5U)
929 #define PVR_PDS_VERTEX_FLAGS_DRAW_INDEX_REQUIRED BITFIELD_BIT(6U)
931 #define PVR_PDS_VERTEX_DMA_FLAGS_INSTANCE_RATE BITFIELD_BIT(0U)
/third_party/mesa3d/src/asahi/compiler/
H A Dagx_compiler.h42 AGX_DBG_MSGS = BITFIELD_BIT(0),
43 AGX_DBG_SHADERS = BITFIELD_BIT(1),
44 AGX_DBG_SHADERDB = BITFIELD_BIT(2),
45 AGX_DBG_VERBOSE = BITFIELD_BIT(3),
46 AGX_DBG_INTERNAL = BITFIELD_BIT(4),
47 AGX_DBG_NOVALIDATE = BITFIELD_BIT(5),
/third_party/mesa3d/src/gallium/drivers/asahi/
H A Dagx_state.h142 AGX_DIRTY_VERTEX = BITFIELD_BIT(0),
143 AGX_DIRTY_VIEWPORT = BITFIELD_BIT(1),
144 AGX_DIRTY_SCISSOR_ZBIAS = BITFIELD_BIT(2),

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