Searched refs:AreConsecutive (Results 1 - 8 of 8) sorted by relevance
| /third_party/vixl/test/aarch64/ |
| H A D | test-api-aarch64.cc | 514 VIXL_CHECK(AreConsecutive(b0, NoVReg)); in TEST()
515 VIXL_CHECK(AreConsecutive(b1, b2)); in TEST()
516 VIXL_CHECK(AreConsecutive(b3, b4, b5)); in TEST()
517 VIXL_CHECK(AreConsecutive(b6, b7, b8, b9)); in TEST()
518 VIXL_CHECK(AreConsecutive(h10, NoVReg)); in TEST()
519 VIXL_CHECK(AreConsecutive(h11, h12)); in TEST()
520 VIXL_CHECK(AreConsecutive(h13, h14, h15)); in TEST()
521 VIXL_CHECK(AreConsecutive(h16, h17, h18, h19)); in TEST()
522 VIXL_CHECK(AreConsecutive(s20, NoVReg)); in TEST()
523 VIXL_CHECK(AreConsecutive(s2 in TEST()
[all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 284 bool AreConsecutive(const VRegister& reg1, const VRegister& reg2, in AreConsecutive() function
2156 DCHECK(AreConsecutive(vn, vn2)); in tbl()
2166 DCHECK(AreConsecutive(vn, vn2, vn3)); in tbl()
2177 DCHECK(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
2190 DCHECK(AreConsecutive(vn, vn2)); in tbx()
2200 DCHECK(AreConsecutive(vn, vn2, vn3)); in tbx()
2211 DCHECK(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
2350 DCHECK(AreConsecutive(vt, vt2)); in ld1()
2359 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld1()
2370 DCHECK(AreConsecutive(v in ld1()
[all...] |
| H A D | register-arm64.h | 536 // AreConsecutive returns true if all of the specified VRegisters are
540 V8_EXPORT_PRIVATE bool AreConsecutive(const VRegister& reg1,
|
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 342 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbl()
355 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbl()
369 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
389 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbx()
402 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbx()
416 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
1706 VIXL_ASSERT(AreConsecutive(rs, rs1)); \
1707 VIXL_ASSERT(AreConsecutive(rt, rt1)); \
2600 VIXL_ASSERT(AreConsecutive(vt, vt2)); in ld1()
2612 VIXL_ASSERT(AreConsecutive(v in ld1()
[all...] |
| H A D | registers-aarch64.h | 1073 // AreConsecutive returns true if all of the specified registers are
1078 bool AreConsecutive(const CPURegister& reg1,
|
| H A D | assembler-sve-aarch64.cc | 4078 VIXL_ASSERT(AreConsecutive(zt1, zt2)); \
4091 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3)); \
4105 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4)); \
5193 VIXL_ASSERT(AreConsecutive(zt1, zt2)); \
5206 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3)); \
5220 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4)); \
5587 VIXL_ASSERT(CPUHas(CPUFeatures::kSVE2) && AreConsecutive(zn, zm)); in ext()
5954 VIXL_ASSERT(AreConsecutive(zn1, zn2)); in splice_con()
8970 VIXL_ASSERT(AreConsecutive(zn1, zn2)); in tbl()
|
| H A D | macro-assembler-sve-aarch64.cc | 2150 if (CPUHas(CPUFeatures::kSVE2) && AreConsecutive(zn, zm) && !zd.Aliases(zn)) { in Splice()
|
| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 2534 if (src1 != src2 && !AreConsecutive(src1, src2)) { in emit_i8x16_shuffle()
2538 DCHECK(AreConsecutive(src1, src2)); in emit_i8x16_shuffle()
|
Completed in 41 milliseconds