/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 479 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 488 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? 559 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 565 if (AddrMode == ARMII::AddrModeT2_so) { 575 AddrMode = ARMII::AddrModeT2_i12; 580 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) { 594 } else if (AddrMode == ARMII::AddrMode5) { 608 } else if (AddrMode [all...] |
H A D | ARMBaseRegisterInfo.cpp | 500 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in getFrameIndexInstrOffset() local 504 switch (AddrMode) { in getFrameIndexInstrOffset() 686 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in isFrameOffsetLegal() local 692 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) in isFrameOffsetLegal() 698 switch (AddrMode) { in isFrameOffsetLegal()
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H A D | ARMISelLowering.h | 369 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 377 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 380 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 384 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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H A D | ThumbRegisterInfo.cpp | 371 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 382 if (AddrMode != ARMII::AddrModeT1_s)
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
H A D | MSP430Disassembler.cpp | 142 enum AddrMode { enum 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() 181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() 187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { in DecodeSrcAddrModeII() 193 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() 205 static const uint8_t *getDecoderTable(AddrMode SrcAM, unsigned Words) { in getDecoderTable() 234 AddrMode SrcAM = DecodeSrcAddrModeI(Insn); 235 AddrMode DstAM = DecodeDstAddrMode(Insn); 289 AddrMode SrcAM = DecodeSrcAddrModeII(Insn);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 2177 /// This is an extended version of TargetLowering::AddrMode 2179 struct ExtAddrMode : public TargetLowering::AddrMode { 2239 // An AddrMode is trivial if it involves no calculation i.e. it is just a base 2242 // An AddrMode is (BaseGV + BaseReg + BaseOffs + ScaleReg * Scale) so it is in isTrivial() 2865 ExtAddrMode &AddrMode; member in __anon23996::AddressingModeMatcher 2898 MemoryInst(MI), AddrMode(AM), InsertedInsts(InsertedInsts), in AddressingModeMatcher() 3209 /// Get the combined AddrMode 3214 /// Add a new AddrMode if it's compatible with the AddrModes we already 3276 // A single AddrMode can trivially be combined. in combineAddrModes() 3591 /// Return true and update AddrMode i 4860 ExtAddrMode AddrMode = AddrModes.getAddrMode(); optimizeMemoryInst() local 5429 TargetLowering::AddrMode AddrMode; splitLargeGEPOffsets() local [all...] |
/third_party/vixl/src/aarch32/ |
H A D | operands-aarch32.h | 637 explicit MemOperand(Register rn, AddrMode addrmode = Offset) in MemOperand() 654 MemOperand(Register rn, int32_t offset, AddrMode addrmode = Offset) in MemOperand() 664 MemOperand(Register rn, Sign sign, int32_t offset, AddrMode addrmode = Offset) in MemOperand() 681 MemOperand(Register rn, Sign sign, Register rm, AddrMode addrmode = Offset) in MemOperand() 695 MemOperand(Register rn, Register rm, AddrMode addrmode = Offset) in MemOperand() 715 AddrMode addrmode = Offset) in MemOperand() 731 MemOperand(Register rn, Register rm, Shift shift, AddrMode addrmode = Offset) in MemOperand() 754 AddrMode addrmode = Offset) in MemOperand() 775 AddrMode addrmode = Offset) in MemOperand() 799 AddrMode GetAddrMod in GetShiftAmount() [all...] |
H A D | macro-assembler-aarch32.cc | 317 AddrMode addrmode) { in GetOffsetMask() 1733 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 1818 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 1955 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 2046 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 2123 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 2196 AddrMode addrmode = operand.GetAddrMode(); in Delegate()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMBaseInfo.h | 185 enum AddrMode { enum 210 inline static const char *AddrModeToString(AddrMode addrmode) { in AddrModeToString() 299 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.h | 184 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 185 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 238 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 239 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/vixl/src/aarch64/ |
H A D | operands-aarch64.h | 396 AddrMode addrmode = Offset); 405 MemOperand(Register base, const Operand& offset, AddrMode addrmode = Offset); 417 AddrMode GetAddrMode() const { return addrmode_; } in GetAddrMode() 471 AddrMode addrmode_;
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H A D | operands-aarch64.cc | 236 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode) in MemOperand() 285 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode) in MemOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.h | 73 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonBaseInfo.h | 35 enum AddrMode { enum
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/third_party/node/deps/v8/src/codegen/arm/ |
H A D | assembler-arm.h | 197 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset); 202 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset); 208 AddrMode am = Offset); 211 AddrMode am = Offset) { in PointerAddressFromSmiKey() 228 AddrMode am() const { return am_; } in am() 240 AddrMode am_; // bits P, U, and W 251 explicit NeonMemOperand(Register rn, AddrMode am = Offset, int align = 0);
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H A D | constants-arm.h | 257 enum AddrMode { enum
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.h | 67 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.h | 91 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 124 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
H A D | IceInstARM32.h | 88 enum AddrMode { enum in Ice::ARM32::OperandARM32Mem 107 AddrMode Mode = Offset) { in create() 115 AddrMode Mode = Offset) { in create() 124 AddrMode getAddrMode() const { return Mode; } in getAddrMode() 152 ConstantInteger32 *ImmOffset, AddrMode Mode); 154 ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode); 161 AddrMode Mode;
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H A D | IceInstMIPS32.h | 121 enum AddrMode { Offset }; enum in Ice::MIPS32::OperandMIPS32Mem 130 Operand *ImmOffset, AddrMode Mode = Offset) { in create() 137 AddrMode getAddrMode() const { return Mode; } in getAddrMode() 162 Str << "] AddrMode=="; 172 AddrMode Mode); 176 const AddrMode Mode;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.h | 68 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 435 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 444 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/node/deps/v8/src/execution/arm64/ |
H A D | simulator-arm64.h | 1494 void LoadStoreHelper(Instruction* instr, int64_t offset, AddrMode addrmode); 1495 void LoadStorePairHelper(Instruction* instr, AddrMode addrmode); 1497 AddrMode addrmode); 1498 void LoadStoreWriteBack(unsigned addr_reg, int64_t offset, AddrMode addrmode); 1500 AddrMode addr_mode); 1502 AddrMode addr_mode);
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/third_party/node/deps/v8/src/codegen/arm64/ |
H A D | instructions-arm64.h | 64 enum AddrMode { Offset, PreIndex, PostIndex }; enum
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