Searched refs:Addpl (Results 1 - 4 of 4) sorted by relevance
| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 178 void MacroAssembler::Addpl(const Register& xd, in Addpl() function in vixl::aarch64::MacroAssembler
220 // `Addpl(sp, sp, 33)` requires five instructions, even though it's only just in Addpl()
334 // For all possible values of vl_divisor, we can simply use `Addpl`. This in CalculateSVEAddress()
337 Addpl(xd, base, offset * (kZRegBitsPerPRegBit / vl_divisor)); in CalculateSVEAddress()
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| H A D | macro-assembler-aarch64.h | 3663 void Addpl(const Register& xd, const Register& xn, int64_t multiplier);
5764 Addpl(xd, xzr, multiplier); in Rdpl()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-sve-aarch64.cc | 5258 // Addpl(xd, xzr, ...).
5398 __ Addpl(x0, x30, 0);
5399 __ Addpl(x1, x30, 1);
5400 __ Addpl(x2, x30, 31);
5401 __ Addpl(x3, x30, -1);
5402 __ Addpl(x4, x30, -32);
5406 __ Addpl(x5, x30, 32);
5407 __ Addpl(x6, x30, -33);
5410 __ Addpl(x7, x30, 0x007fffffffffffff);
5411 __ Addpl(x
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| H A D | test-disasm-sve-aarch64.cc | 191 // SVE_MUL_VL variants use `Addpl`, which has its own tests, but in TEST()
6096 // There is no `rdpl` instruction. `Rdpl` is implemented as `Addpl` (with in TEST()
6127 COMPARE_MACRO(Addpl(x22, x22, -3), "addpl x22, x22, #-3"); in TEST()
6128 COMPARE_MACRO(Addpl(x10, x11, 8), "addpl x10, x11, #8"); in TEST()
6129 COMPARE_MACRO(Addpl(x7, sp, 31), "addpl x7, sp, #31"); in TEST()
6131 // Otherwise, if the multiplier is a multiple of 8, `Addpl` will pass through in TEST()
6133 COMPARE_MACRO(Addpl(sp, x0, 48), "addvl sp, x0, #6"); in TEST()
6134 COMPARE_MACRO(Addpl(x2, sp, -48), "addvl x2, sp, #-6"); in TEST()
6136 // If xn is xzr, `Addpl` behaves like `Rdpl`. in TEST()
6137 COMPARE_MACRO(Addpl(x in TEST()
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