Searched refs:ADDS (Results 1 - 7 of 7) sorted by relevance
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 534 ADDS = ADD | AddSubSetFlagsBit,
539 #define ADD_SUB_OP_LIST(V) V(ADD), V(ADDS), V(SUB), V(SUBS)
582 ADCS_w = AddSubWithCarryFixed | ADDS,
583 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 56 ADDS,
|
| H A D | AArch64ISelLowering.cpp | 1251 case AArch64ISD::ADDS: return "AArch64ISD::ADDS"; in getTargetNodeName()
1730 Opcode = AArch64ISD::ADDS; in emitComparison()
1735 Opcode = AArch64ISD::ADDS; in emitComparison()
2157 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095. in getAArch64Cmp()
2218 Opc = AArch64ISD::ADDS; in getAArch64XALUOOp()
2222 Opc = AArch64ISD::ADDS; in getAArch64XALUOOp()
2438 Opc = AArch64ISD::ADDS; in LowerADDC_ADDE_SUBC_SUBE()
9456 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
12039 if (CmpOpc != AArch64ISD::ADDS in performBRCONDCombine()
[all...] |
| /third_party/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 664 ADDS = ADD | AddSubSetFlagsBit, enumerator
671 V(ADDS), \
716 ADCS_w = AddSubWithCarryFixed | ADDS,
717 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
|
| H A D | simulator-aarch64.cc | 3898 case ADDS: { in Simulator()
|
| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeARM_T2_32.c | 100 #define ADDS 0x1800 macro
847 return push_inst16(compiler, ADDS | RD3(dst) | RN3(arg1) | RM3(arg2)); in emit_op_imm()
|
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 1806 case ADDS: {
|
Completed in 61 milliseconds