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Searched refs:write_reg (Results 1 - 25 of 356) sorted by relevance

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/kernel/linux/linux-5.10/drivers/staging/fbtft/
H A Dfb_upd161704.c31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ in init_display()
49 write_reg(pa in init_display()
[all...]
H A Dfb_bd663474.c31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
44 write_reg(par, 0x100, 0x3120); in init_display()
47 write_reg(pa in init_display()
[all...]
H A Dfb_ili9320.c27 write_reg(par, 0x0000); in read_devicecode()
50 write_reg(par, 0x00E5, 0x8000); in init_display()
53 write_reg(par, 0x0000, 0x0001); in init_display()
56 write_reg(par, 0x0001, 0x0100); in init_display()
59 write_reg(par, 0x0002, 0x0700); in init_display()
62 write_reg(par, 0x0004, 0x0000); in init_display()
65 write_reg(par, 0x0008, 0x0202); in init_display()
68 write_reg(par, 0x0009, 0x0000); in init_display()
71 write_reg(par, 0x000A, 0x0000); in init_display()
74 write_reg(pa in init_display()
[all...]
H A Dfb_s6d1121.c33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
41 write_reg(par, 0x0013, 0x674F); in init_display()
42 write_reg(pa in init_display()
[all...]
H A Dfb_ssd1289.c30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
38 write_reg(par, 0x02, 0x0600); in init_display()
39 write_reg(par, 0x10, 0x0000); in init_display()
40 write_reg(pa in init_display()
[all...]
H A Dfb_ili9325.c96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
101 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
104 write_reg(par, 0x000A, 0x0000); /* FMARK function */ in init_display()
105 write_reg(pa in init_display()
[all...]
H A Dfb_hx8347d.c28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
36 write_reg(par, 0x27, 0xA3); in init_display()
39 write_reg(pa in init_display()
[all...]
H A Dfb_ra8875.c55 write_reg(par, 0x88, 0x0A); in init_display()
56 write_reg(par, 0x89, 0x02); in init_display()
59 write_reg(par, 0x10, 0x0C); in init_display()
61 write_reg(par, 0x04, 0x03); in init_display()
64 write_reg(par, 0x14, 0x27); in init_display()
65 write_reg(par, 0x15, 0x00); in init_display()
66 write_reg(par, 0x16, 0x05); in init_display()
67 write_reg(par, 0x17, 0x04); in init_display()
68 write_reg(par, 0x18, 0x03); in init_display()
70 write_reg(pa in init_display()
[all...]
H A Dfb_tinylcd.c24 write_reg(par, 0xB0, 0x80); in init_display()
25 write_reg(par, 0xC0, 0x0A, 0x0A); in init_display()
26 write_reg(par, 0xC1, 0x45, 0x07); in init_display()
27 write_reg(par, 0xC2, 0x33); in init_display()
28 write_reg(par, 0xC5, 0x00, 0x42, 0x80); in init_display()
29 write_reg(par, 0xB1, 0xD0, 0x11); in init_display()
30 write_reg(par, 0xB4, 0x02); in init_display()
31 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); in init_display()
32 write_reg(par, 0xB7, 0x07); in init_display()
33 write_reg(pa in init_display()
[all...]
H A Dfb_ssd1306.c21 * write_reg() caveat:
24 * write_reg(par, val1, val2);
27 * write_reg(par, val1);
28 * write_reg(par, val2);
46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
50 write_reg(par, 0x80); in init_display()
53 write_reg(par, 0xA8); in init_display()
55 write_reg(par, 0x3F); in init_display()
57 write_reg(pa in init_display()
[all...]
H A Dfb_seps525.c104 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03); in init_display()
107 write_reg(par, SEPS525_REDUCE_CURRENT, 0x00); in init_display()
110 write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00); in init_display()
112 write_reg(par, SEPS525_OSC_CTL, 0x01); in init_display()
114 write_reg(par, SEPS525_CLOCK_DIV, 0x90); in init_display()
116 write_reg(par, SEPS525_IREF, 0x01); in init_display()
119 write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04); in init_display()
120 write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05); in init_display()
121 write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05); in init_display()
124 write_reg(pa in init_display()
[all...]
H A Dfb_ssd1305.c22 * write_reg() caveat:
25 * write_reg(par, val1, val2);
28 * write_reg(par, val1);
29 * write_reg(par, val2);
47 write_reg(par, 0xAE); in init_display()
50 write_reg(par, 0xD5); in init_display()
51 write_reg(par, 0x80); in init_display()
54 write_reg(par, 0xA8); in init_display()
56 write_reg(par, 0x3F); in init_display()
58 write_reg(pa in init_display()
[all...]
/kernel/linux/linux-6.6/drivers/staging/fbtft/
H A Dfb_upd161704.c31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ in init_display()
49 write_reg(pa in init_display()
[all...]
H A Dfb_bd663474.c31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
44 write_reg(par, 0x100, 0x3120); in init_display()
47 write_reg(pa in init_display()
[all...]
H A Dfb_ili9320.c26 write_reg(par, 0x0000); in read_devicecode()
49 write_reg(par, 0x00E5, 0x8000); in init_display()
52 write_reg(par, 0x0000, 0x0001); in init_display()
55 write_reg(par, 0x0001, 0x0100); in init_display()
58 write_reg(par, 0x0002, 0x0700); in init_display()
61 write_reg(par, 0x0004, 0x0000); in init_display()
64 write_reg(par, 0x0008, 0x0202); in init_display()
67 write_reg(par, 0x0009, 0x0000); in init_display()
70 write_reg(par, 0x000A, 0x0000); in init_display()
73 write_reg(pa in init_display()
[all...]
H A Dfb_s6d1121.c33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
41 write_reg(par, 0x0013, 0x674F); in init_display()
42 write_reg(pa in init_display()
[all...]
H A Dfb_ssd1289.c30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
38 write_reg(par, 0x02, 0x0600); in init_display()
39 write_reg(par, 0x10, 0x0000); in init_display()
40 write_reg(pa in init_display()
[all...]
H A Dfb_hx8347d.c28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
36 write_reg(par, 0x27, 0xA3); in init_display()
39 write_reg(pa in init_display()
[all...]
H A Dfb_ili9325.c96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
101 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
104 write_reg(par, 0x000A, 0x0000); /* FMARK function */ in init_display()
105 write_reg(pa in init_display()
[all...]
H A Dfb_ra8875.c55 write_reg(par, 0x88, 0x0A); in init_display()
56 write_reg(par, 0x89, 0x02); in init_display()
59 write_reg(par, 0x10, 0x0C); in init_display()
61 write_reg(par, 0x04, 0x03); in init_display()
64 write_reg(par, 0x14, 0x27); in init_display()
65 write_reg(par, 0x15, 0x00); in init_display()
66 write_reg(par, 0x16, 0x05); in init_display()
67 write_reg(par, 0x17, 0x04); in init_display()
68 write_reg(par, 0x18, 0x03); in init_display()
70 write_reg(pa in init_display()
[all...]
H A Dfb_tinylcd.c24 write_reg(par, 0xB0, 0x80); in init_display()
25 write_reg(par, 0xC0, 0x0A, 0x0A); in init_display()
26 write_reg(par, 0xC1, 0x45, 0x07); in init_display()
27 write_reg(par, 0xC2, 0x33); in init_display()
28 write_reg(par, 0xC5, 0x00, 0x42, 0x80); in init_display()
29 write_reg(par, 0xB1, 0xD0, 0x11); in init_display()
30 write_reg(par, 0xB4, 0x02); in init_display()
31 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); in init_display()
32 write_reg(par, 0xB7, 0x07); in init_display()
33 write_reg(pa in init_display()
[all...]
H A Dfb_ssd1306.c21 * write_reg() caveat:
24 * write_reg(par, val1, val2);
27 * write_reg(par, val1);
28 * write_reg(par, val2);
46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
50 write_reg(par, 0x80); in init_display()
53 write_reg(par, 0xA8); in init_display()
55 write_reg(par, 0x3F); in init_display()
57 write_reg(pa in init_display()
[all...]
H A Dfb_seps525.c104 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03); in init_display()
107 write_reg(par, SEPS525_REDUCE_CURRENT, 0x00); in init_display()
110 write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00); in init_display()
112 write_reg(par, SEPS525_OSC_CTL, 0x01); in init_display()
114 write_reg(par, SEPS525_CLOCK_DIV, 0x90); in init_display()
116 write_reg(par, SEPS525_IREF, 0x01); in init_display()
119 write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04); in init_display()
120 write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05); in init_display()
121 write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05); in init_display()
124 write_reg(pa in init_display()
[all...]
/kernel/linux/linux-5.10/arch/sh/boards/mach-kfr2r09/
H A Dlcd_wqvga.c65 static void write_reg(void *sohandle, in write_reg() function
82 write_reg(sohandle, so, 1, data[i]); in write_data()
91 write_reg(sohandle, so, 0, 0xb0); in read_device_code()
92 write_reg(sohandle, so, 1, 0x00); in read_device_code()
95 write_reg(sohandle, so, 0, 0xb1); in read_device_code()
96 write_reg(sohandle, so, 1, 0x00); in read_device_code()
99 write_reg(sohandle, so, 0, 0xbf); in read_device_code()
117 write_reg(sohandle, so, 0, 0x2c); in write_memory_start()
130 write_reg(sohandle, so, 1, 0x00); in clear_memory()
137 write_reg(sohandl in display_on()
[all...]
/kernel/linux/linux-6.6/arch/sh/boards/mach-kfr2r09/
H A Dlcd_wqvga.c65 static void write_reg(void *sohandle, in write_reg() function
82 write_reg(sohandle, so, 1, data[i]); in write_data()
91 write_reg(sohandle, so, 0, 0xb0); in read_device_code()
92 write_reg(sohandle, so, 1, 0x00); in read_device_code()
95 write_reg(sohandle, so, 0, 0xb1); in read_device_code()
96 write_reg(sohandle, so, 1, 0x00); in read_device_code()
99 write_reg(sohandle, so, 0, 0xbf); in read_device_code()
117 write_reg(sohandle, so, 0, 0x2c); in write_memory_start()
130 write_reg(sohandle, so, 1, 0x00); in clear_memory()
137 write_reg(sohandl in display_on()
[all...]

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