| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| H A D | mmu_context.h | 43 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in cpu_set_reserved_ttbr0() local
45 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0()
143 /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */ in cpu_replace_ttbr1()
189 u64 ttbr; in update_saved_ttbr0() local
195 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in update_saved_ttbr0()
197 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
199 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| H A D | assembler.h | 540 * ttbr: Value of ttbr to set, modified.
542 .macro offset_ttbr1, ttbr, tmp variable
547 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET variable
557 .macro restore_ttbr1, ttbr
559 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET variable
568 * ttbr: returns the TTBR value
570 .macro phys_to_ttbr, ttbr, phy variable
572 orr \\ttbr, \\phys, \\phys, lsr #46 global() variable
573 and \\ttbr, \\ttbr, #TTBR_BADDR_MASK_52 global() variable
[all...] |
| H A D | uaccess.h | 111 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
114 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
115 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
117 write_sysreg(ttbr - PAGE_SIZE, ttbr0_el1); in __uaccess_ttbr0_disable()
120 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| /kernel/linux/linux-6.6/arch/arm64/include/asm/ |
| H A D | mmu_context.h | 44 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in cpu_set_reserved_ttbr0_nosync() local
46 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0_nosync()
162 /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */ in cpu_replace_ttbr1()
216 u64 ttbr; in update_saved_ttbr0() local
222 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in update_saved_ttbr0()
224 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
226 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| H A D | uaccess.h | 61 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
64 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
65 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
67 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); in __uaccess_ttbr0_disable()
69 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| H A D | assembler.h | 482 * in the tlb, switch the ttbr to a zero page when we invalidate the old
596 * ttbr: Value of ttbr to set, modified.
598 .macro offset_ttbr1, ttbr, tmp variable
603 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET variable
613 * ttbr: returns the TTBR value
615 .macro phys_to_ttbr, ttbr, phys variable
617 orr \ttbr, \phys, \phys, lsr #46 variable
618 and \ttbr, \ttb variable
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
| H A D | msm_iommu.c | 24 phys_addr_t ttbr; member
101 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params()
110 if (ttbr) in msm_iommu_pagetable_params()
111 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
203 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
100 msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, int *asid) msm_iommu_pagetable_params() argument
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| H A D | msm_mmu.h | 58 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| H A D | proc-fns.h | 160 u64 ttbr; \
162 : "=r" (ttbr)); \
163 ttbr; \
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| /kernel/linux/linux-6.6/arch/arm/include/asm/ |
| H A D | proc-fns.h | 158 u64 ttbr; \
160 : "=r" (ttbr)); \
161 ttbr; \
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/ |
| H A D | msm_iommu.c | 27 phys_addr_t ttbr; member
173 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params()
182 if (ttbr) in msm_iommu_pagetable_params()
183 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
309 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
172 msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, int *asid) msm_iommu_pagetable_params() argument
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| H A D | msm_mmu.h | 60 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| /kernel/linux/linux-6.6/include/linux/ |
| H A D | io-pgtable.h | 106 u64 ttbr; member
132 u32 ttbr; member
144 u64 ttbr[4]; member
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| /kernel/linux/linux-5.10/include/linux/ |
| H A D | io-pgtable.h | 107 u64 ttbr; member
133 u32 ttbr; member
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| /kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu.c | 508 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
509 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
511 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
513 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
517 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
519 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
522 cb->ttbr[ in arm_smmu_init_context_bank()
[all...] |
| /kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu.c | 482 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
483 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
485 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
487 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
491 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
493 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
496 cb->ttbr[ in arm_smmu_init_context_bank()
[all...] |
| H A D | arm-smmu-qcom.c | 156 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
168 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
169 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| H A D | ipmmu-vmsa.c | 370 u64 ttbr; in ipmmu_domain_setup_context() local
374 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
375 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
376 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| H A D | mtk_iommu.c | 397 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
819 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_resume()
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| /kernel/linux/linux-6.6/drivers/iommu/ |
| H A D | ipmmu-vmsa.c | 355 u64 ttbr; in ipmmu_domain_setup_context() local
359 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
360 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
361 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| H A D | apple-dart.c | 146 #define DART_TTBR(dart, sid, idx) ((dart)->hw->ttbr + \
180 u64 ttbr; member
563 pgtbl_cfg->apple_dart_cfg.ttbr[i]); in apple_dart_setup_translation()
1184 .ttbr = DART_T8020_TTBR,
1209 .ttbr = DART_T8020_TTBR,
1234 .ttbr = DART_T8110_TTBR,
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.c | 98 phys_addr_t ttbr; in a6xx_set_pagetable() local
105 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
110 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
113 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
124 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
125 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); in a6xx_set_pagetable()
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| /kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | arm-smmu-v3-sva.c | 127 cd->ttbr = virt_to_phys(mm->pgd); in arm_smmu_alloc_shared_cd()
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| /kernel/liteos_a/arch/arm/arm/src/ |
| H A D | los_arch_mmu.c | 927 UINT32 ttbr; in LOS_ArchMmuContextSwitch() local
930 ttbr = MMU_TTBRx_FLAGS | (archMmu->physTtb); in LOS_ArchMmuContextSwitch()
934 ttbr = 0; in LOS_ArchMmuContextSwitch()
944 OsArmWriteTtbr0(ttbr); in LOS_ArchMmuContextSwitch()
977 /* ttbr address should be 16KByte align */ in OsSwitchTmpTTB()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.c | 106 phys_addr_t ttbr; in a6xx_set_pagetable() local
113 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
127 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
130 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
141 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
142 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); in a6xx_set_pagetable()
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