| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| H A D | intel_sseu.c | 11 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, in intel_sseu_set_info() argument
14 sseu->max_slices = max_slices; in intel_sseu_set_info()
15 sseu->max_subslices = max_subslices; in intel_sseu_set_info()
16 sseu->max_eus_per_subslice = max_eus_per_subslice; in intel_sseu_set_info()
18 sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); in intel_sseu_set_info()
19 GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE); in intel_sseu_set_info()
20 sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); in intel_sseu_set_info()
21 GEM_BUG_ON(sseu in intel_sseu_set_info()
25 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) intel_sseu_subslice_total() argument
35 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice) intel_sseu_get_subslices() argument
49 intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, u32 ss_mask) intel_sseu_set_subslices() argument
58 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) intel_sseu_subslices_per_slice() argument
63 sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, int subslice) sseu_eu_idx() argument
71 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int subslice) sseu_get_eus() argument
84 sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, u16 eu_mask) sseu_set_eus() argument
94 compute_eu_total(const struct sseu_dev_info *sseu) compute_eu_total() argument
104 gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en, u32 ss_en, u16 eu_en) gen11_compute_sseu_info() argument
131 struct sseu_dev_info *sseu = >->info.sseu; gen12_sseu_info_init() local
166 struct sseu_dev_info *sseu = >->info.sseu; gen11_sseu_info_init() local
195 struct sseu_dev_info *sseu = >->info.sseu; gen10_sseu_info_init() local
271 struct sseu_dev_info *sseu = >->info.sseu; cherryview_sseu_info_init() local
328 struct sseu_dev_info *sseu = >->info.sseu; gen9_sseu_info_init() local
433 struct sseu_dev_info *sseu = >->info.sseu; bdw_sseu_info_init() local
519 struct sseu_dev_info *sseu = >->info.sseu; hsw_sseu_info_init() local
608 const struct sseu_dev_info *sseu = >->info.sseu; intel_sseu_make_rpcs() local
719 intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) intel_sseu_dump() argument
740 intel_sseu_print_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) intel_sseu_print_topology() argument
[all...] |
| H A D | intel_sseu_debugfs.c | 11 static void sseu_copy_subslices(const struct sseu_dev_info *sseu, in sseu_copy_subslices() argument
14 int offset = slice * sseu->ss_stride; in sseu_copy_subslices()
16 memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); in sseu_copy_subslices()
20 struct sseu_dev_info *sseu) in cherryview_sseu_device_status()
40 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
41 sseu->subslice_mask[0] |= BIT(ss); in cherryview_sseu_device_status()
46 sseu->eu_total += eu_cnt; in cherryview_sseu_device_status()
47 sseu->eu_per_subslice = max_t(unsigned int, in cherryview_sseu_device_status()
48 sseu in cherryview_sseu_device_status()
19 cherryview_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) cherryview_sseu_device_status() argument
53 gen10_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) gen10_sseu_device_status() argument
113 gen9_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) gen9_sseu_device_status() argument
176 bdw_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) bdw_sseu_device_status() argument
202 i915_print_sseu_info(struct seq_file *m, bool is_available_info, bool has_pooled_eu, const struct sseu_dev_info *sseu) i915_print_sseu_info() argument
248 struct sseu_dev_info sseu; intel_sseu_status() local
[all...] |
| H A D | intel_sseu.h | 59 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) in intel_sseu_from_device_info() argument
62 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
63 .subslice_mask = sseu->subslice_mask[0], in intel_sseu_from_device_info()
64 .min_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
65 .max_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
72 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
78 GEM_BUG_ON(ss_idx >= sseu->ss_stride); in intel_sseu_has_subslice()
80 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; in intel_sseu_has_subslice()
85 void intel_sseu_set_info(struct sseu_dev_info *sseu, u
[all...] |
| H A D | intel_context_sseu.c | 18 const struct intel_sseu sseu) in gen8_emit_rpcs_config()
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
66 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
76 const struct intel_sseu sseu) in intel_context_reconfigure_sseu()
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
90 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
92 ce->sseu in intel_context_reconfigure_sseu()
16 gen8_emit_rpcs_config(struct i915_request *rq, const struct intel_context *ce, const struct intel_sseu sseu) gen8_emit_rpcs_config() argument
75 intel_context_reconfigure_sseu(struct intel_context *ce, const struct intel_sseu sseu) intel_context_reconfigure_sseu() argument
[all...] |
| H A D | intel_gt_types.h | 123 struct sseu_dev_info sseu; member
|
| H A D | intel_context_types.h | 123 /** sseu: Control eu/slice partitioning */
124 struct intel_sseu sseu; member
|
| H A D | intel_workarounds.c | 451 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
460 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
1085 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; in wa_init_mcr() local
1119 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { in wa_init_mcr()
1130 slice = fls(sseu->slice_mask) - 1; in wa_init_mcr()
1131 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); in wa_init_mcr()
1135 intel_sseu_get_subslices(sseu, slice), l3_en); in wa_init_mcr()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| H A D | intel_sseu.c | 14 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, in intel_sseu_set_info() argument
17 sseu->max_slices = max_slices; in intel_sseu_set_info()
18 sseu->max_subslices = max_subslices; in intel_sseu_set_info()
19 sseu->max_eus_per_subslice = max_eus_per_subslice; in intel_sseu_set_info()
23 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) in intel_sseu_subslice_total() argument
27 if (sseu->has_xehp_dss) in intel_sseu_subslice_total()
28 return bitmap_weight(sseu->subslice_mask.xehp, in intel_sseu_subslice_total()
29 XEHP_BITMAP_BITS(sseu->subslice_mask)); in intel_sseu_subslice_total()
31 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++) in intel_sseu_subslice_total()
32 total += hweight8(sseu in intel_sseu_subslice_total()
38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice) intel_sseu_get_hsw_subslices() argument
47 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int subslice) sseu_get_eus() argument
58 sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, u16 eu_mask) sseu_set_eus() argument
70 compute_eu_total(const struct sseu_dev_info *sseu) compute_eu_total() argument
94 intel_sseu_copy_eumask_to_user(void __user *to, const struct sseu_dev_info *sseu) intel_sseu_copy_eumask_to_user() argument
128 intel_sseu_copy_ssmask_to_user(void __user *to, const struct sseu_dev_info *sseu) intel_sseu_copy_ssmask_to_user() argument
150 gen11_compute_sseu_info(struct sseu_dev_info *sseu, u32 ss_en, u16 eu_en) gen11_compute_sseu_info() argument
167 xehp_compute_sseu_info(struct sseu_dev_info *sseu, u16 eu_en) xehp_compute_sseu_info() argument
210 struct sseu_dev_info *sseu = >->info.sseu; xehp_sseu_info_init() local
258 struct sseu_dev_info *sseu = >->info.sseu; gen12_sseu_info_init() local
299 struct sseu_dev_info *sseu = >->info.sseu; gen11_sseu_info_init() local
333 struct sseu_dev_info *sseu = >->info.sseu; cherryview_sseu_info_init() local
386 struct sseu_dev_info *sseu = >->info.sseu; gen9_sseu_info_init() local
491 struct sseu_dev_info *sseu = >->info.sseu; bdw_sseu_info_init() local
577 struct sseu_dev_info *sseu = >->info.sseu; hsw_sseu_info_init() local
665 const struct sseu_dev_info *sseu = >->info.sseu; intel_sseu_make_rpcs() local
776 intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) intel_sseu_dump() argument
813 sseu_print_hsw_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) sseu_print_hsw_topology() argument
833 sseu_print_xehp_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) sseu_print_xehp_topology() argument
848 intel_sseu_print_topology(struct drm_i915_private *i915, const struct sseu_dev_info *sseu, struct drm_printer *p) intel_sseu_print_topology() argument
861 intel_sseu_print_ss_info(const char *type, const struct sseu_dev_info *sseu, struct seq_file *m) intel_sseu_print_ss_info() argument
[all...] |
| H A D | intel_sseu_debugfs.c | 16 struct sseu_dev_info *sseu) in cherryview_sseu_device_status()
36 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
37 sseu->subslice_mask.hsw[0] |= BIT(ss); in cherryview_sseu_device_status()
42 sseu->eu_total += eu_cnt; in cherryview_sseu_device_status()
43 sseu->eu_per_subslice = max_t(unsigned int, in cherryview_sseu_device_status()
44 sseu->eu_per_subslice, eu_cnt); in cherryview_sseu_device_status()
50 struct sseu_dev_info *sseu) in gen11_sseu_device_status()
58 for (s = 0; s < info->sseu.max_slices; s++) { in gen11_sseu_device_status()
82 for (s = 0; s < info->sseu.max_slices; s++) { in gen11_sseu_device_status()
87 sseu in gen11_sseu_device_status()
15 cherryview_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) cherryview_sseu_device_status() argument
49 gen11_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) gen11_sseu_device_status() argument
109 gen9_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) gen9_sseu_device_status() argument
168 bdw_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) bdw_sseu_device_status() argument
193 i915_print_sseu_info(struct seq_file *m, bool is_available_info, bool has_pooled_eu, const struct sseu_dev_info *sseu) i915_print_sseu_info() argument
235 struct sseu_dev_info *sseu; intel_sseu_status() local
[all...] |
| H A D | intel_sseu.h | 109 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) in intel_sseu_from_device_info() argument
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
113 .subslice_mask = sseu->subslice_mask.hsw[0], in intel_sseu_from_device_info()
114 .min_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
115 .max_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
125 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
126 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
129 if (sseu->has_xehp_dss) in intel_sseu_has_subslice()
130 return test_bit(subslice, sseu in intel_sseu_has_subslice()
141 intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize, int groupnum) intel_sseu_find_first_xehp_dss() argument
[all...] |
| H A D | intel_context_sseu.c | 18 const struct intel_sseu sseu) in gen8_emit_rpcs_config()
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
66 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
76 const struct intel_sseu sseu) in intel_context_reconfigure_sseu()
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
90 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
92 ce->sseu in intel_context_reconfigure_sseu()
16 gen8_emit_rpcs_config(struct i915_request *rq, const struct intel_context *ce, const struct intel_sseu sseu) gen8_emit_rpcs_config() argument
75 intel_context_reconfigure_sseu(struct intel_context *ce, const struct intel_sseu sseu) intel_context_reconfigure_sseu() argument
[all...] |
| H A D | intel_gt_mcr.h | 57 intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
58 intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
|
| H A D | intel_workarounds.c | 548 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
557 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
1118 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in gen9_wa_init_mcr() local
1135 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1136 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
1137 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); in gen9_wa_init_mcr()
1279 const struct sseu_dev_info *sseu = >->info.sseu; in icl_wa_init_mcr() local
1283 GEM_BUG_ON(hweight8(sseu in icl_wa_init_mcr()
1310 const struct sseu_dev_info *sseu = >->info.sseu; xehp_init_mcr() local
[all...] |
| H A D | intel_gt_types.h | 267 struct sseu_dev_info sseu; member
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| H A D | i915_query.c | 32 static int fill_topology_info(const struct sseu_dev_info *sseu, in fill_topology_info() argument
38 int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); in fill_topology_info()
39 int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); in fill_topology_info()
42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in fill_topology_info()
44 if (sseu->max_slices == 0) in fill_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in fill_topology_info()
48 subslice_length = sseu->max_slices * ss_stride; in fill_topology_info()
49 eu_length = sseu->max_slices * sseu->max_subslices * eu_stride; in fill_topology_info()
59 topo.max_slices = sseu in fill_topology_info()
93 const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu; query_topology_info() local
104 const struct sseu_dev_info *sseu; query_geometry_subslices() local
[all...] |
| H A D | i915_getparam.c | 20 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in i915_getparam_ioctl() local
78 value = intel_sseu_subslice_total(sseu); in i915_getparam_ioctl()
83 value = sseu->eu_total; in i915_getparam_ioctl()
100 value = sseu->min_eu_in_pool; in i915_getparam_ioctl()
166 value = sseu->slice_mask; in i915_getparam_ioctl()
176 value = intel_sseu_get_hsw_subslices(sseu, 0); in i915_getparam_ioctl()
|
| H A D | i915_perf_types.h | 446 * @sseu: sseu configuration selected to run while perf is active,
449 struct intel_sseu sseu; member
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_query.c | 34 const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu; in query_topology_info() local
42 if (sseu->max_slices == 0) in query_topology_info()
45 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in query_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in query_topology_info()
48 subslice_length = sseu->max_slices * sseu->ss_stride; in query_topology_info()
49 eu_length = sseu->max_slices * sseu->max_subslices * sseu in query_topology_info()
[all...] |
| H A D | i915_getparam.c | 15 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; in i915_getparam_ioctl() local
73 value = intel_sseu_subslice_total(sseu); in i915_getparam_ioctl()
78 value = sseu->eu_total; in i915_getparam_ioctl()
95 value = sseu->min_eu_in_pool; in i915_getparam_ioctl()
147 value = sseu->slice_mask; in i915_getparam_ioctl()
152 value = sseu->subslice_mask[0]; in i915_getparam_ioctl()
|
| H A D | i915_perf_types.h | 413 * @sseu: sseu configuration selected to run while perf is active,
416 struct intel_sseu sseu; member
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_context.c | 818 struct intel_sseu *sseu; in set_proto_ctx_sseu() local
854 sseu = &pe->sseu; in set_proto_ctx_sseu()
864 sseu = &pc->legacy_rcs_sseu; in set_proto_ctx_sseu()
867 ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu); in set_proto_ctx_sseu()
960 struct intel_sseu sseu) in intel_context_set_gem()
990 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
991 ret = intel_context_reconfigure_sseu(ce, sseu); in intel_context_set_gem()
1114 struct intel_sseu sseu = {}; in default_engines() local
1133 sseu in default_engines()
958 intel_context_set_gem(struct intel_context *ce, struct i915_gem_context *ctx, struct intel_sseu sseu) intel_context_set_gem() argument
1995 struct intel_sseu sseu; set_sseu() local
[all...] |
| H A D | i915_gem_context_types.h | 124 /** @sseu: Client-set SSEU parameters */
125 struct intel_sseu sseu; member
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_context.c | 1153 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1158 ret = intel_engine_reset(ce->engine, "sseu"); in __sseu_finish()
1194 struct intel_sseu sseu) in __sseu_test()
1205 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1210 hweight32(sseu.slice_mask), spin); in __sseu_test()
1255 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1258 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1265 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1268 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1272 hweight32(engine->sseu in __igt_ctx_sseu()
1190 __sseu_test(const char *name, unsigned int flags, struct intel_context *ce, struct drm_i915_gem_object *obj, struct intel_sseu sseu) __sseu_test() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_context.c | 1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1174 ret = intel_engine_reset(ce->engine, "sseu"); in __sseu_finish()
1210 struct intel_sseu sseu) in __sseu_test()
1221 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1226 hweight32(sseu.slice_mask), spin); in __sseu_test()
1271 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1274 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1281 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1284 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1288 hweight32(engine->sseu in __igt_ctx_sseu()
1206 __sseu_test(const char *name, unsigned int flags, struct intel_context *ce, struct drm_i915_gem_object *obj, struct intel_sseu sseu) __sseu_test() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_context.c | 1429 const struct sseu_dev_info *device = >->info.sseu; in i915_gem_user_to_context_sseu()
1529 struct intel_sseu sseu; in set_sseu() local
1563 ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu); in set_sseu()
1567 ret = intel_context_reconfigure_sseu(ce, sseu); in set_sseu()
2245 clone->engines[n]->sseu = ce->sseu; in clone_sseu()
2461 user_sseu.slice_mask = ce->sseu.slice_mask; in get_sseu()
2462 user_sseu.subslice_mask = ce->sseu.subslice_mask; in get_sseu()
2463 user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice; in get_sseu()
2464 user_sseu.max_eus_per_subslice = ce->sseu in get_sseu()
[all...] |