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Searched refs:slice_mask (Results 1 - 25 of 43) sorted by relevance

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/kernel/linux/linux-5.10/arch/powerpc/mm/
H A Dslice.c34 static void slice_print_mask(const char *label, const struct slice_mask *mask) in slice_print_mask()
48 static void slice_print_mask(const char *label, const struct slice_mask *mask) {} in slice_print_mask()
61 struct slice_mask *ret) in slice_range_to_mask()
117 static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret, in slice_mask_for_free()
139 const struct slice_mask *available, in slice_check_range_fits()
188 const struct slice_mask *mask, int psize) in slice_convert()
193 struct slice_mask *psize_mask, *old_mask; in slice_convert()
215 /* Update the slice_mask */ in slice_convert()
234 /* Update the slice_mask */ in slice_convert()
262 const struct slice_mask *availabl in slice_scan_available()
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/kernel/linux/linux-6.6/arch/powerpc/mm/book3s64/
H A Dslice.c34 static void slice_print_mask(const char *label, const struct slice_mask *mask) in slice_print_mask()
48 static void slice_print_mask(const char *label, const struct slice_mask *mask) {} in slice_print_mask()
61 struct slice_mask *ret) in slice_range_to_mask()
117 static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret, in slice_mask_for_free()
139 const struct slice_mask *available, in slice_check_range_fits()
188 const struct slice_mask *mask, int psize) in slice_convert()
193 struct slice_mask *psize_mask, *old_mask; in slice_convert()
215 /* Update the slice_mask */ in slice_convert()
234 /* Update the slice_mask */ in slice_convert()
262 const struct slice_mask *availabl in slice_scan_available()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_sseu_debugfs.c40 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
91 sseu->slice_mask |= BIT(s); in gen10_sseu_device_status()
144 sseu->slice_mask |= BIT(s); in gen9_sseu_device_status()
183 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; in bdw_sseu_device_status()
185 if (sseu->slice_mask) { in bdw_sseu_device_status()
187 for (s = 0; s < fls(sseu->slice_mask); s++) in bdw_sseu_device_status()
194 for (s = 0; s < fls(sseu->slice_mask); s++) { in bdw_sseu_device_status()
211 sseu->slice_mask); in i915_print_sseu_info()
213 hweight8(sseu->slice_mask)); in i915_print_sseu_info()
216 for (s = 0; s < fls(sseu->slice_mask); in i915_print_sseu_info()
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H A Dintel_sseu.c117 sseu->slice_mask |= BIT(s); in gen11_compute_sseu_info()
203 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> in gen10_sseu_info_init()
277 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init()
335 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in gen9_sseu_info_init()
354 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init()
409 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; in gen9_sseu_info_init()
440 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in bdw_sseu_info_init()
466 if (!(sseu->slice_mask & BIT(s))) in bdw_sseu_info_init()
511 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; in bdw_sseu_info_init()
533 sseu->slice_mask in hsw_sseu_info_init()
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H A Dintel_sseu.h27 u8 slice_mask; member
52 u8 slice_mask; member
62 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c156 sseu->slice_mask |= BIT(0); in gen11_compute_sseu_info()
172 sseu->slice_mask |= BIT(0); in xehp_compute_sseu_info()
338 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init()
393 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in gen9_sseu_info_init()
412 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init()
467 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; in gen9_sseu_info_init()
498 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in bdw_sseu_info_init()
524 if (!(sseu->slice_mask & BIT(s))) in bdw_sseu_info_init()
569 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; in bdw_sseu_info_init()
591 sseu->slice_mask in hsw_sseu_info_init()
885 unsigned long slice_mask = 0; intel_slicemask_from_xehp_dssmask() local
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H A Dintel_sseu_debugfs.c36 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
87 sseu->slice_mask |= BIT(s); in gen11_sseu_device_status()
140 sseu->slice_mask |= BIT(s); in gen9_sseu_device_status()
175 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; in bdw_sseu_device_status()
177 if (sseu->slice_mask) { in bdw_sseu_device_status()
179 for (s = 0; s < fls(sseu->slice_mask); s++) in bdw_sseu_device_status()
185 for (s = 0; s < fls(sseu->slice_mask); s++) { in bdw_sseu_device_status()
201 sseu->slice_mask); in i915_print_sseu_info()
203 hweight8(sseu->slice_mask)); in i915_print_sseu_info()
H A Dintel_sseu.h69 u8 slice_mask; member
102 u8 slice_mask; member
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
H A Dintel_workarounds.c1135 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1283 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1311 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr() local
1342 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, in xehp_init_mcr()
1356 if (slice_mask & lncf_mask) { in xehp_init_mcr()
1357 slice_mask &= lncf_mask; in xehp_init_mcr()
1362 if (slice_mask & gt->info.mslice_mask) { in xehp_init_mcr()
1363 slice_mask &= gt->info.mslice_mask; in xehp_init_mcr()
1367 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) in xehp_init_mcr()
1370 slice = __ffs(slice_mask); in xehp_init_mcr()
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/kernel/linux/linux-5.10/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h696 struct slice_mask { struct
709 struct slice_mask mask_64k;
711 struct slice_mask mask_4k;
713 struct slice_mask mask_16m;
714 struct slice_mask mask_16g;
H A Dmmu.h165 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) in slice_mask_for_size()
/kernel/linux/linux-6.6/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h708 struct slice_mask { struct
721 struct slice_mask mask_64k;
723 struct slice_mask mask_4k;
725 struct slice_mask mask_16m;
726 struct slice_mask mask_16g;
H A Dmmu.h169 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) in slice_mask_for_size()
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
H A Dicp_qat_fw_loader_handle.h18 unsigned int slice_mask; member
/kernel/linux/linux-6.6/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_fw_loader_handle.h19 unsigned int slice_mask; member
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c990 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
1899 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1911 if (overflows_type(user->slice_mask, context->slice_mask) || in i915_gem_user_to_context_sseu()
1920 if (user->slice_mask & ~device->slice_mask) in i915_gem_user_to_context_sseu()
1929 context->slice_mask = user->slice_mask; in i915_gem_user_to_context_sseu()
1936 unsigned int hw_s = hweight8(device->slice_mask); in i915_gem_user_to_context_sseu()
1938 unsigned int req_s = hweight8(context->slice_mask); in i915_gem_user_to_context_sseu()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1433 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1445 if (overflows_type(user->slice_mask, context->slice_mask) || in i915_gem_user_to_context_sseu()
1454 if (user->slice_mask & ~device->slice_mask) in i915_gem_user_to_context_sseu()
1463 context->slice_mask = user->slice_mask; in i915_gem_user_to_context_sseu()
1470 unsigned int hw_s = hweight8(device->slice_mask); in i915_gem_user_to_context_sseu()
1472 unsigned int req_s = hweight8(context->slice_mask); in i915_gem_user_to_context_sseu()
2461 user_sseu.slice_mask in get_sseu()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_query.c45 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in query_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in query_topology_info()
76 &sseu->slice_mask, slice_length)) in query_topology_info()
H A Di915_getparam.c147 value = sseu->slice_mask; in i915_getparam_ioctl()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_query.c42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in fill_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in fill_topology_info()
73 &sseu->slice_mask, slice_length)) in fill_topology_info()
H A Di915_getparam.c166 value = sseu->slice_mask; in i915_getparam_ioctl()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c511 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask); in intel_dbuf_slice_size()
515 skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask, in skl_ddb_entry_for_slices() argument
520 if (!slice_mask) { in skl_ddb_entry_for_slices()
526 ddb->start = (ffs(slice_mask) - 1) * slice_size; in skl_ddb_entry_for_slices()
527 ddb->end = fls(slice_mask) * slice_size; in skl_ddb_entry_for_slices()
533 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask) in mbus_ddb_offset() argument
537 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) in mbus_ddb_offset()
538 slice_mask = BIT(DBUF_S1); in mbus_ddb_offset()
539 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) in mbus_ddb_offset()
540 slice_mask in mbus_ddb_offset()
552 u8 slice_mask = 0; skl_ddb_dbuf_slice_mask() local
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H A Dintel_display_device.c449 .dbuf.slice_mask = BIT(DBUF_S1),
473 .dbuf.slice_mask = BIT(DBUF_S1), \
513 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
566 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
654 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
H A Dintel_display_device.h103 u8 slice_mask; member
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c160 hweight8(gt->info.sseu.slice_mask); in __guc_ads_init()

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