Searched refs:sdm_cfg1 (Results 1 - 2 of 2) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| H A D | dsi_pll_28nm.c | 136 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; in dsi_pll_28nm_clk_set_rate() local
184 sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); in dsi_pll_28nm_clk_set_rate()
185 sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; in dsi_pll_28nm_clk_set_rate()
189 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( in dsi_pll_28nm_clk_set_rate()
197 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0); in dsi_pll_28nm_clk_set_rate()
203 DBG("sdm_cfg1=%d", sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
216 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_28nm.c | 123 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; in dsi_pll_28nm_clk_set_rate() local
171 sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); in dsi_pll_28nm_clk_set_rate()
172 sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; in dsi_pll_28nm_clk_set_rate()
176 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( in dsi_pll_28nm_clk_set_rate()
184 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0); in dsi_pll_28nm_clk_set_rate()
190 DBG("sdm_cfg1=%d", sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
203 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
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