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Searched refs:roce_write (Results 1 - 5 of 5) sorted by relevance

/kernel/linux/linux-5.10/drivers/infiniband/hw/hns/
H A Dhns_roce_hw_v1.c414 roce_write(to_hr_dev(ibqp->device), in hns_roce_v1_post_recv()
450 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); in hns_roce_set_db_event_mode()
541 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); in hns_roce_set_db_ext_mode()
558 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val); in hns_roce_set_sdb()
575 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val); in hns_roce_set_odb()
589 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept); in hns_roce_set_sdb_ext()
590 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful); in hns_roce_set_sdb_ext()
594 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12)); in hns_roce_set_sdb_ext()
610 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val); in hns_roce_set_sdb_ext()
628 roce_write(hr_de in hns_roce_set_odb_ext()
[all...]
H A Dhns_roce_common.h36 #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) macro
H A Dhns_roce_hw_v2.c1127 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); in hns_roce_cmq_init_regs()
1128 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, in hns_roce_cmq_init_regs()
1130 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, in hns_roce_cmq_init_regs()
1132 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); in hns_roce_cmq_init_regs()
1133 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); in hns_roce_cmq_init_regs()
1135 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); in hns_roce_cmq_init_regs()
1136 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, in hns_roce_cmq_init_regs()
1138 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, in hns_roce_cmq_init_regs()
1140 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); in hns_roce_cmq_init_regs()
1141 roce_write(hr_de in hns_roce_cmq_init_regs()
[all...]
/kernel/linux/linux-6.6/drivers/infiniband/hw/hns/
H A Dhns_roce_common.h37 #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) macro
H A Dhns_roce_hw_v2.c1183 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); in init_csq()
1184 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); in init_csq()
1185 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, in init_csq()
1189 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); in init_csq()
1190 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); in init_csq()
1293 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); in __hns_roce_cmq_send()
6068 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, in abnormal_interrupt_basic()
6079 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); in abnormal_interrupt_basic()
6251 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + in hns_roce_v2_int_mask_enable()
6254 roce_write(hr_de in hns_roce_v2_int_mask_enable()
[all...]

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