| /kernel/linux/linux-6.6/tools/testing/selftests/user_events/ |
| H A D | abi_test.c | 50 static int reg_enable(void *enable, int size, int bit) in reg_enable() function
113 ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0)); in TEST_F()
133 ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0)); in TEST_F()
134 ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 31)); in TEST_F()
135 ASSERT_NE(0, reg_enable(&self->check, sizeof(int), 32)); in TEST_F()
141 ASSERT_EQ(0, reg_enable(&self->check_long, sizeof(long), 63)); in TEST_F()
142 ASSERT_NE(0, reg_enable(&self->check_long, sizeof(long), 64)); in TEST_F()
147 ASSERT_NE(0, reg_enable(&self->check, 1, 0)); in TEST_F()
148 ASSERT_NE(0, reg_enable(&self->check, 2, 0)); in TEST_F()
149 ASSERT_NE(0, reg_enable( in TEST_F()
[all...] |
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| H A D | irq-bcm6345-l1.c | 91 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() function
133 pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); in bcm6345_l1_irq_handle()
156 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); in __bcm6345_l1_unmask()
168 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); in __bcm6345_l1_mask()
262 __raw_writel(0, cpu->map_base + reg_enable(intc, i)); in bcm6345_l1_init_one()
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| H A D | irq-bcm2835.c | 70 static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
152 intc.enable[b] = base + reg_enable[b]; in armctrl_of_init()
|
| /kernel/linux/linux-6.6/drivers/irqchip/ |
| H A D | irq-bcm6345-l1.c | 90 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() function
131 pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); in bcm6345_l1_irq_handle()
151 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); in __bcm6345_l1_unmask()
163 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); in __bcm6345_l1_mask()
260 __raw_writel(0, cpu->map_base + reg_enable(intc, i)); in bcm6345_l1_init_one()
|
| H A D | irq-bcm2835.c | 70 static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
152 intc.enable[b] = base + reg_enable[b]; in armctrl_of_init()
|
| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| H A D | qcom-cpufreq-hw.c | 26 u32 reg_enable; member
256 .reg_enable = 0x0,
264 .reg_enable = 0x0,
338 if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { in qcom_cpufreq_hw_cpu_init()
|
| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| H A D | hw_breakpoint.c | 228 int i, max_slots, ctrl_reg, val_reg, reg_enable; in hw_breakpoint_control() local
238 reg_enable = !debug_info->bps_disabled; in hw_breakpoint_control()
245 reg_enable = !debug_info->wps_disabled; in hw_breakpoint_control()
268 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); in hw_breakpoint_control()
|
| /kernel/linux/linux-6.6/arch/arm64/kernel/ |
| H A D | hw_breakpoint.c | 228 int i, max_slots, ctrl_reg, val_reg, reg_enable; in hw_breakpoint_control() local
238 reg_enable = !debug_info->bps_disabled; in hw_breakpoint_control()
245 reg_enable = !debug_info->wps_disabled; in hw_breakpoint_control()
268 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); in hw_breakpoint_control()
|
| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| H A D | qcom-cpufreq-hw.c | 34 u32 reg_enable; member
399 .reg_enable = 0x0,
409 .reg_enable = 0x0,
542 if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) { in qcom_cpufreq_hw_cpu_init()
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