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Searched refs:pwrstctrl_offs (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-omap2/
H A Dpowerdomains33xx_data.c28 .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
59 .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
69 .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
79 .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
122 .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
165 .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
H A Dprm33xx.c153 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_next_pwrst()
161 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_read_next_pwrst()
183 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_lowpwrstchange()
204 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_logic_retst()
228 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_read_logic_retst()
245 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_mem_onst()
260 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_mem_retst()
288 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_read_mem_retst()
348 pwrdm->pwrstctrl_offs); in am33xx_pwrdm_save_context()
364 pwrdm->pwrstctrl_offs); in am33xx_pwrdm_restore_context()
[all...]
H A Dprm44xx.c687 pwrdm->pwrstctrl_offs); in omap4_pwrdm_save_context()
709 pwrdm->pwrstctrl_offs); in omap4_pwrdm_restore_context()
714 pwrdm->pwrstctrl_offs); in omap4_pwrdm_restore_context()
H A Dpowerdomain.h91 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
94 * in @pwrstctrl_offs
95 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
96 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
99 * in @pwrstctrl_offs
132 const u8 pwrstctrl_offs; member
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
H A Dpowerdomains33xx_data.c20 .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
51 .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
61 .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
71 .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
114 .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
157 .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
H A Dprm33xx.c145 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_next_pwrst()
153 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_read_next_pwrst()
175 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_lowpwrstchange()
196 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_logic_retst()
220 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_read_logic_retst()
237 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_mem_onst()
252 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_set_mem_retst()
280 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); in am33xx_pwrdm_read_mem_retst()
340 pwrdm->pwrstctrl_offs); in am33xx_pwrdm_save_context()
356 pwrdm->pwrstctrl_offs); in am33xx_pwrdm_restore_context()
[all...]
H A Dprm44xx.c687 pwrdm->pwrstctrl_offs); in omap4_pwrdm_save_context()
709 pwrdm->pwrstctrl_offs); in omap4_pwrdm_restore_context()
714 pwrdm->pwrstctrl_offs); in omap4_pwrdm_restore_context()
H A Dpowerdomain.h91 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
94 * in @pwrstctrl_offs
95 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
96 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
99 * in @pwrstctrl_offs
132 const u8 pwrstctrl_offs; member

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