Searched refs:pwr_mgmt_1 (Results 1 - 4 of 4) sorted by relevance
/kernel/linux/linux-5.10/drivers/iio/imu/inv_mpu6050/ |
H A D | inv_mpu_core.c | 51 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1, 74 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1, 95 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1, 261 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val); in inv_mpu6050_pwr_mgmt_1_write() 262 return regmap_write(st->map, st->reg->pwr_mgmt_1, val); in inv_mpu6050_pwr_mgmt_1_write() 1325 result = regmap_write(st->map, st->reg->pwr_mgmt_1, in inv_check_and_setup_chip()
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H A D | inv_mpu_iio.h | 38 * @pwr_mgmt_1: Controls chip's power state and clock source. 60 u8 pwr_mgmt_1; member
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/kernel/linux/linux-6.6/drivers/iio/imu/inv_mpu6050/ |
H A D | inv_mpu_core.c | 54 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1, 77 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1, 98 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1, 304 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val); in inv_mpu6050_pwr_mgmt_1_write() 305 return regmap_write(st->map, st->reg->pwr_mgmt_1, val); in inv_mpu6050_pwr_mgmt_1_write() 1376 result = regmap_write(st->map, st->reg->pwr_mgmt_1, in inv_check_and_setup_chip()
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H A D | inv_mpu_iio.h | 40 * @pwr_mgmt_1: Controls chip's power state and clock source. 62 u8 pwr_mgmt_1; member
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