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Searched refs:pll_value (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-5.10/drivers/staging/sm750fb/
H A Dddk750_chip.h42 struct pll_value { struct
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
98 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL);
H A Dddk750_chip.c58 struct pll_value pll; in set_chip_clock()
313 struct pll_value *pll) in sm750_calc_pll_value()
385 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL) in sm750_format_pll_reg()
H A Dddk750_mode.c79 struct pll_value *pll) in programModeRegisters()
212 struct pll_value pll; in ddk750_setModeTiming()
/kernel/linux/linux-6.6/drivers/staging/sm750fb/
H A Dddk750_chip.h42 struct pll_value { struct
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
98 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL);
H A Dddk750_chip.c58 struct pll_value pll; in set_chip_clock()
313 struct pll_value *pll) in sm750_calc_pll_value()
385 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL) in sm750_format_pll_reg()
H A Dddk750_mode.c79 struct pll_value *pll) in programModeRegisters()
212 struct pll_value pll; in ddk750_setModeTiming()
/kernel/linux/linux-5.10/arch/m68k/q40/
H A Dconfig.c267 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
269 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
284 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | in q40_set_rtc_pll()
/kernel/linux/linux-6.6/arch/m68k/q40/
H A Dconfig.c256 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
258 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
273 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | in q40_set_rtc_pll()
/kernel/linux/linux-5.10/drivers/video/fbdev/geode/
H A Dvideo_cs5530.c25 u32 pll_value; member
76 value = cs5530_pll_table[0].pll_value; in cs5530_set_dclk_frequency()
84 value = cs5530_pll_table[i].pll_value; in cs5530_set_dclk_frequency()
/kernel/linux/linux-6.6/drivers/video/fbdev/geode/
H A Dvideo_cs5530.c25 u32 pll_value; member
76 value = cs5530_pll_table[0].pll_value; in cs5530_set_dclk_frequency()
84 value = cs5530_pll_table[i].pll_value; in cs5530_set_dclk_frequency()
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci-pci-gli.c150 u32 pll_value; in gli_set_9750() local
160 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
182 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; in gli_set_9750()
183 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; in gli_set_9750()
184 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, in gli_set_9750()
186 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, in gli_set_9750()
210 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
H A Drtc.h26 int pll_value; member
/kernel/linux/linux-5.10/include/uapi/linux/
H A Drtc.h48 * pll_value is used to get or set current value of correction,
53 * +ve pll_value means clock will run faster by
54 * pll_value*pll_posmult/pll_clock
55 * -ve pll_value means clock will run slower by
56 * pll_value*pll_negmult/pll_clock
61 int pll_value; /* get/set correction value */ member
/kernel/linux/linux-6.6/include/uapi/linux/
H A Drtc.h49 * pll_value is used to get or set current value of correction,
54 * +ve pll_value means clock will run faster by
55 * pll_value*pll_posmult/pll_clock
56 * -ve pll_value means clock will run slower by
57 * pll_value*pll_negmult/pll_clock
62 int pll_value; /* get/set correction value */ member
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
H A Drtc.h41 int pll_value; member
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
H A Drtc.h41 int pll_value; member
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsdhci-pci-gli.c267 u32 pll_value; in gli_set_9750() local
277 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
299 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; in gli_set_9750()
300 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; in gli_set_9750()
301 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, in gli_set_9750()
303 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, in gli_set_9750()
327 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()

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