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Searched refs:pll9 (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1977 PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9); in bxt_ddi_pll_enable()
2087 hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2088 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2224 dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5); in bxt_ddi_set_dpll_hw_state()
2334 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", in bxt_dump_hw_state()
2343 hw_state->pll9, in bxt_dump_hw_state()
H A Dintel_display.c5335 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); in intel_pipe_config_compare()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1896 temp |= pll->state.hw_state.pll9; in bxt_ddi_pll_enable()
2013 hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2014 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2174 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; in bxt_ddi_set_dpll_hw_state()
2269 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", in bxt_dump_hw_state()
2278 hw_state->pll9, in bxt_dump_hw_state()
H A Dintel_display.c14007 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); in intel_pipe_config_compare()

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