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Searched refs:pipe_mask (Results 1 - 25 of 48) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c183 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
196 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
232 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
293 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
334 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
356 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
370 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
386 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
404 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
424 .__runtime_defaults.pipe_mask
[all...]
H A Dintel_display_device.h41 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
69 #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
81 u8 pipe_mask; member
H A Dintel_dpll_mgr.c226 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll() local
235 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
236 drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
239 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
272 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll() local
282 if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
295 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
326 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll()
339 shared_dpll[i].pipe_mask, in intel_find_shared_dpll()
4439 u8 pipe_mask; verify_single_dpll_state() local
4500 u8 pipe_mask = BIT(crtc->pipe); intel_shared_dpll_state_verify() local
[all...]
H A Dintel_display_irq.h34 void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask);
35 void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask);
H A Dintel_ddi.c758 u8 *pipe_mask, bool *is_dp_mst) in intel_ddi_get_encoder_pipes()
768 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
790 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
793 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
796 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
835 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
838 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
843 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { in intel_ddi_get_encoder_pipes()
845 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", in intel_ddi_get_encoder_pipes()
847 *pipe_mask); in intel_ddi_get_encoder_pipes()
757 intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, u8 *pipe_mask, bool *is_dp_mst) intel_ddi_get_encoder_pipes() argument
876 u8 pipe_mask; intel_ddi_get_hw_state() local
2031 u8 pipe_mask; intel_ddi_sanitize_encoder_pll_mapping() local
[all...]
H A Dintel_dpll_mgr.h239 * @pipe_mask: mask of pipes using this DPLL, active or not
241 u8 pipe_mask; member
H A Dg4x_hdmi.c756 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
758 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
760 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
H A Dintel_display.h224 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
280 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
284 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
H A Dintel_dp.h47 u8 *pipe_mask);
H A Dintel_dp.c4261 u8 *pipe_mask) in intel_dp_get_active_pipes()
4268 *pipe_mask = 0; in intel_dp_get_active_pipes()
4299 *pipe_mask |= BIT(crtc->pipe); in intel_dp_get_active_pipes()
4320 u8 pipe_mask; in intel_dp_retrain_link() local
4334 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in intel_dp_retrain_link()
4338 if (pipe_mask == 0) in intel_dp_retrain_link()
4347 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4358 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4375 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4393 u8 *pipe_mask) in intel_dp_prep_phy_test()
4259 intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) intel_dp_get_active_pipes() argument
4391 intel_dp_prep_phy_test(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) intel_dp_prep_phy_test() argument
4444 u8 pipe_mask; intel_dp_do_phy_test() local
[all...]
H A Dg4x_dp.c1362 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1364 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1366 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
H A Dintel_crt.c1053 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1055 crt->base.pipe_mask = ~0; in intel_crt_init()
H A Dintel_lvds.c924 encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
926 encoder->pipe_mask = ~0; in intel_lvds_init()
H A Dintel_display_irq.c1484 u8 pipe_mask) in gen8_irq_power_well_post_enable()
1499 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
1508 u8 pipe_mask) in gen8_irq_power_well_pre_disable()
1520 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
1483 gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask) gen8_irq_power_well_post_enable() argument
1507 gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, u8 pipe_mask) gen8_irq_power_well_pre_disable() argument
H A Dintel_tc.c1614 u8 pipe_mask; in reset_link_commit() local
1621 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in reset_link_commit()
1625 if (!pipe_mask) in reset_link_commit()
1628 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { in reset_link_commit()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_pci.c162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
183 .pipe_mask = BIT(PIPE_A), \
225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
398 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
450 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
504 .pipe_mask = 0, /* legal, last one wins */
513 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
610 .pipe_mask
[all...]
H A Dintel_device_info.c456 info->pipe_mask = 0; in intel_device_info_runtime_init()
460 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
467 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
471 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
475 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
480 info->pipe_mask &= ~BIT(PIPE_D); in intel_device_info_runtime_init()
H A Di915_irq.h100 u8 pipe_mask);
102 u8 pipe_mask);
H A Dintel_device_info.h178 u8 pipe_mask; member
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_ddi.c1940 u8 *pipe_mask, bool *is_dp_mst) in intel_ddi_get_encoder_pipes()
1950 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
1972 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
1975 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
1978 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
2016 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
2019 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
2024 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { in intel_ddi_get_encoder_pipes()
2026 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", in intel_ddi_get_encoder_pipes()
2028 *pipe_mask); in intel_ddi_get_encoder_pipes()
1939 intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, u8 *pipe_mask, bool *is_dp_mst) intel_ddi_get_encoder_pipes() argument
2057 u8 pipe_mask; intel_ddi_get_hw_state() local
3017 u8 pipe_mask; icl_sanitize_encoder_pll_mapping() local
[all...]
H A Dintel_crt.c1045 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1047 crt->base.pipe_mask = ~0; in intel_crt_init()
H A Dintel_lvds.c909 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
911 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
H A Dintel_display_types.h134 u8 pipe_mask; member
1509 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); in intel_get_crtc_for_pipe()
/kernel/linux/linux-5.10/drivers/usb/renesas_usbhs/
H A Dcommon.c276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
/kernel/linux/linux-6.6/drivers/usb/renesas_usbhs/
H A Dcommon.c276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()

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