| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 47 const unsigned int pipe_idx) in dml32_rq_dlg_get_rq_reg()
49 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml32_rq_dlg_get_rq_reg()
74 dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); in dml32_rq_dlg_get_rq_reg()
85 dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA in dml32_rq_dlg_get_rq_reg()
86 mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA in dml32_rq_dlg_get_rq_reg()
129 detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; in dml32_rq_dlg_get_rq_reg()
132 pipe_idx); in dml32_rq_dlg_get_rq_reg()
141 num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
149 rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); in dml32_rq_dlg_get_rq_reg()
150 rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); in dml32_rq_dlg_get_rq_reg()
43 dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx) dml32_rq_dlg_get_rq_reg() argument
206 dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx) dml32_rq_dlg_get_dlg_reg() argument
[all...] |
| H A D | dcn32_fpu.c | 325 uint32_t i, pipe_idx; in dcn32_helper_populate_phantom_dlg_params() local
329 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
336 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
337 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
338 pipes[pipe_idx].pipe.dest.vupdate_offset = in dcn32_helper_populate_phantom_dlg_params()
339 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
340 pipes[pipe_idx].pipe.dest.vupdate_width = in dcn32_helper_populate_phantom_dlg_params()
341 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
342 pipes[pipe_idx].pipe.dest.vready_offset = in dcn32_helper_populate_phantom_dlg_params()
343 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
545 unsigned int i, pipe_idx; dcn32_set_phantom_stream_timing() local
674 unsigned int i, pipe_idx; dcn32_assign_subvp_pipe() local
1097 uint32_t i, pipe_idx; subvp_validate_static_schedulability() local
1350 int i, pipe_idx, active_hubp_count = 0; dcn32_calculate_dlg_params() local
1559 int pipe_idx = sec_pipe->pipe_idx; dcn32_split_stream_for_mpc_or_odm() local
1650 int pipe_cnt, i, pipe_idx; dcn32_internal_validate_bw() local
1964 int i, pipe_idx, vlevel_temp = 0; dcn32_calculate_wm_and_dlg_fpu() local
3082 unsigned int i, pipe_idx; dcn32_assign_fpo_vactive_candidate() local
3110 unsigned int i, pipe_idx; dcn32_find_vactive_pipe() local
[all...] |
| H A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx);
59 * pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
68 const unsigned int pipe_idx);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 1312 int pipe_idx) in dcn20_acquire_dsc()
1316 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1323 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1324 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1468 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1473 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1474 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1475 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1309 dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, int pipe_idx) dcn20_acquire_dsc() argument
1552 int pipe_idx = secondary_pipe->pipe_idx; dcn20_split_stream_for_mpc() local
1837 int i, pipe_idx, vlevel_split; dcn20_validate_apply_pipe_split_flags() local
2029 int pipe_cnt, i, pipe_idx, vlevel; dcn20_fast_validate_bw() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.c | 856 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params()
867 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
868 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
869 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
870 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
871 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
958 int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA in dml_rq_dlg_get_dlg_params()
959 int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA in dml_rq_dlg_get_dlg_params()
961 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml_rq_dlg_get_dlg_params()
962 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mh in dml_rq_dlg_get_dlg_params()
852 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml_rq_dlg_get_dlg_params() argument
1560 dml31_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml31_rq_dlg_get_dlg_reg() argument
[all...] |
| H A D | dcn31_fpu.c | 486 int i, pipe_idx, total_det = 0, active_hubp_count = 0; in dcn31_calculate_wm_and_dlg_fp() local
527 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
534 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn31_calculate_wm_and_dlg_fp()
535 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn31_calculate_wm_and_dlg_fp()
538 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
539 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
541 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
542 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
543 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx] in dcn31_calculate_wm_and_dlg_fp()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.c | 941 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params()
952 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
953 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
954 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
955 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
956 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1043 unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA in dml_rq_dlg_get_dlg_params()
1044 unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA in dml_rq_dlg_get_dlg_params()
1046 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml_rq_dlg_get_dlg_params()
1047 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mh in dml_rq_dlg_get_dlg_params()
937 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml_rq_dlg_get_dlg_params() argument
1648 dml314_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml314_rq_dlg_get_dlg_reg() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 833 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params()
841 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
845 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1117 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
829 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en) dml_rq_dlg_get_dlg_params() argument
1657 dml21_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml21_rq_dlg_get_dlg_reg() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 833 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params()
841 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
845 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1117 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
829 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en) dml_rq_dlg_get_dlg_params() argument
1657 dml21_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml21_rq_dlg_get_dlg_reg() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 418 int i, pipe_idx; in dcn301_calculate_wm_and_dlg_fp() local
453 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_calculate_wm_and_dlg_fp()
457 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
458 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn301_calculate_wm_and_dlg_fp()
461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
462 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
464 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_calculate_wm_and_dlg_fp()
465 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg_fp()
466 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx] in dcn301_calculate_wm_and_dlg_fp()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 1670 int pipe_idx) in dcn20_acquire_dsc()
1674 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1681 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1682 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1870 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1875 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1876 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1877 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1667 dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, int pipe_idx) dcn20_acquire_dsc() argument
1944 int pipe_idx = secondary_pipe->pipe_idx; dcn20_split_stream_for_mpc() local
2656 int i, pipe_idx, vlevel_split; global() local
2848 int pipe_cnt, i, pipe_idx, vlevel; global() local
2962 int pipe_cnt, i, pipe_idx; global() local
3076 int i, pipe_idx; global() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params()
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20v2_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20v2_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20v2_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1029 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
784 dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en) dml20v2_rq_dlg_get_dlg_params() argument
1550 dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml20v2_rq_dlg_get_dlg_reg() argument
[all...] |
| H A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params()
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1028 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
784 dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en) dml20_rq_dlg_get_dlg_params() argument
1549 dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml20_rq_dlg_get_dlg_reg() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params()
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20v2_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20v2_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20v2_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1029 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
784 dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en) dml20v2_rq_dlg_get_dlg_params() argument
1550 dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml20v2_rq_dlg_get_dlg_reg() argument
[all...] |
| H A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params()
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1028 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
784 dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en) dml20_rq_dlg_get_dlg_params() argument
1549 dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml20_rq_dlg_get_dlg_reg() argument
[all...] |
| H A D | dcn20_fpu.c | 1140 int i, pipe_idx, active_hubp_count = 0; in dcn20_calculate_dlg_params() local
1173 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1178 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn20_calculate_dlg_params()
1179 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn20_calculate_dlg_params()
1180 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn20_calculate_dlg_params()
1181 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn20_calculate_dlg_params()
1729 int pipe_cnt, i, pipe_idx; dcn20_calculate_wm() local
2135 dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, int vlevel, int max_mpc_comb, int pipe_idx, bool is_validating_bw) dcn20_fpu_adjust_dppclk() argument
2237 int pipe_cnt, i, pipe_idx; dcn21_calculate_wm() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 57 const unsigned int pipe_idx,
75 const unsigned int pipe_idx);
80 const unsigned int pipe_idx);
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 984 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params()
995 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
996 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
997 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
998 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
999 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
1000 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1142 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1217 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1263 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
981 dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml_rq_dlg_get_dlg_params() argument
1831 dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml30_rq_dlg_get_dlg_reg() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 893 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params()
904 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
905 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
906 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
907 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
908 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
909 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1051 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1126 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1172 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
890 dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml_rq_dlg_get_dlg_params() argument
1742 dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) dml30_rq_dlg_get_dlg_reg() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 305 int pipe_idx = 0; in dc_dmub_srv_populate_fams_pipe_info() local
307 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
312 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
315 fams_pipe_data->pipe_count = pipe_idx; in dc_dmub_srv_populate_fams_pipe_info()
325 int pipe_idx = 0; in dc_dmub_srv_p_state_delegate() local
339 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
353 pipe_idx++; in dc_dmub_srv_p_state_delegate()
550 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; in populate_subvp_cmd_vblank_pipe_info()
677 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
679 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
717 uint32_t i, pipe_idx; dc_dmub_setup_subvp_dmub_command() local
973 dc_send_update_cursor_info_to_dmu( struct pipe_ctx *pCtx, uint8_t pipe_idx) dc_send_update_cursor_info_to_dmu() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc()
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
50 dce60_should_enable_fbc(struct dc *dc, struct dc_state *context, uint32_t *pipe_idx) dce60_should_enable_fbc() argument
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc()
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
50 dce60_should_enable_fbc(struct dc *dc, struct dc_state *context, uint32_t *pipe_idx) dce60_should_enable_fbc() argument
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 1857 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1862 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1863 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1864 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1865 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1866 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1867 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1868 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx] in dcn30_split_stream_for_mpc_or_odm()
1956 int pipe_cnt, i, pipe_idx, vlevel; dcn30_internal_validate_bw() local
2223 int i, pipe_idx; dcn30_calculate_wm_and_dlg_fp() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 1528 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1533 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1534 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1535 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1536 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1537 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1538 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1539 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx] in dcn30_split_stream_for_mpc_or_odm()
1639 int pipe_cnt, i, pipe_idx, vlevel; dcn30_internal_validate_bw() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1511 pipe_ctx->pipe_idx, in resource_build_scaling_params()
1595 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in resource_find_free_secondary_pipe_legacy()
1598 secondary_pipe->pipe_idx = preferred_pipe_idx; in resource_find_free_secondary_pipe_legacy()
1610 secondary_pipe->pipe_idx = i; in resource_find_free_secondary_pipe_legacy()
1632 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx]; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1634 free_pipe_idx = cur_sec_dpp->pipe_idx; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1822 split_pipe->pipe_idx = i; in acquire_first_split_pipe()
1889 int pipe_idx = acquire_first_split_pipe( in acquire_secondary_dpp_pipes_and_add_plane() local
1893 if (pipe_idx >= 0) in acquire_secondary_dpp_pipes_and_add_plane()
1894 sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx]; in acquire_secondary_dpp_pipes_and_add_plane()
2723 int pipe_idx = -1; resource_map_pool_resources() local
4144 reset_sync_context_for_pipe(const struct dc *dc, struct dc_state *context, uint8_t pipe_idx) reset_sync_context_for_pipe() argument
4257 int pipe_idx = sec_pipe->pipe_idx; dc_resource_acquire_secondary_pipe_for_mpc_odm() local
[all...] |