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Searched refs:pipe_count (Results 1 - 25 of 90) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c128 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
173 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
190 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
215 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
309 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
320 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
329 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
339 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
346 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn32_determine_det_override()
359 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; in dcn32_set_det_allocations()
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H A Ddcn32_hwseq.c228 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
347 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
378 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
398 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
606 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
627 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
658 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_mall_sel()
718 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_program_mall_pipe_config()
931 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_init_hw()
1204 for (i = 0; i < dc->res_pool->pipe_count; in dcn32_resync_fifo_dccg_dio()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1109 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1368 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1618 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1663 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1733 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1756 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1778 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1807 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1850 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_apply_pipe_split_flags()
1870 if (plane_count > dc->res_pool->pipe_count / in dcn20_validate_apply_pipe_split_flags()
2233 uint32_t pipe_count = pool->res_cap->num_dwb; dcn20_dwbc_create() local
2256 uint32_t pipe_count = pool->res_cap->num_dwb; dcn20_mmhubbub_create() local
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H A Ddcn20_hwseq.c1799 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1808 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1820 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1835 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1842 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1862 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1871 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1893 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1958 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1968 for (i = 0; i < dc->res_pool->pipe_count; in dcn20_post_unlock_program_front_end()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
H A Ddcn10_hw_sequencer.c94 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
164 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
196 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
221 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
253 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
286 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
328 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
695 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
739 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
766 for (i = 0; i < dc->res_pool->pipe_count; in false_optc_underflow_wa()
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H A Ddcn10_resource.c986 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1374 pool->base.pipe_count = 3; in dcn10_resource_construct()
1554 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1623 pool->base.pipe_count = j; in dcn10_resource_construct()
1629 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1630 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1652 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c134 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
204 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
249 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
303 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
342 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
395 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
510 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c1059 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
1113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1210 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1307 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1400 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1403 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1426 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1429 for (i = 0; i < pipe_count; in program_timing_sync()
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H A Ddc_surface.c150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_resource.c823 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
986 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1274 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1275 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1276 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1277 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1278 pool->pipe_count++; in underlay_create()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1372 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1444 for (i = 0; i < pool->base.pipe_count; in dce110_resource_construct()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_resource.c810 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
883 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
969 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1048 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1110 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1168 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1246 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1308 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1366 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1440 for (i = 0; i < pool->base.pipe_count; in dce83_construct()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c805 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
878 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1039 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1101 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1159 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1237 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1299 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1357 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1431 for (i = 0; i < pool->base.pipe_count; in dce64_construct()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c801 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
874 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1035 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1097 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1155 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1233 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1295 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1353 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1427 for (i = 0; i < pool->base.pipe_count; in dce64_construct()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_resource.c816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
979 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1269 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1270 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1271 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1272 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1273 pool->pipe_count++; in underlay_create()
1367 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1368 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1443 for (i = 0; i < pool->base.pipe_count; in dce110_resource_construct()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_resource.c808 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
881 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
967 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1049 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1111 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1169 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1249 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1311 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1369 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1446 for (i = 0; i < pool->base.pipe_count; in dce83_construct()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_resource.c708 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
710 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
743 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
745 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
963 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
964 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1019 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1094 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1213 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1366 for (i = 0; i < pool->pipe_count; in dcn302_resource_construct()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_resource.c651 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
653 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
686 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
688 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
890 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
891 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
945 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1020 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1136 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1278 for (i = 0; i < pool->pipe_count; in dcn303_resource_construct()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c791 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
816 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
858 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
961 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1030 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1033 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1056 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1059 for (i = 0; i < pipe_count; in program_timing_sync()
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H A Ddc_surface.c150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
163 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1095 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1176 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1216 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1218 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1241 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1243 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1329 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1384 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1511 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1597 for (i = dc->res_pool->pipe_count in dcn30_find_split_pipe()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1483 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1974 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
2013 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2033 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2436 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2482 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2552 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2575 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2597 for (i = 0; i < dc->res_pool->pipe_count;
3349 uint32_t pipe_count = pool->res_cap->num_dwb; global() local
3372 uint32_t pipe_count = pool->res_cap->num_dwb; global() local
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H A Ddcn20_hwseq.c1434 int opp_count = dc->res_pool->pipe_count; in dcn20_update_dchubp_dpp()
1652 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1663 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1676 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1681 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1689 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1700 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1730 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1740 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1825 for (i = 0; i < dc->res_pool->pipe_count; in dcn20_update_bandwidth()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c527 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
562 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
566 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
594 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
666 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
733 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1233 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1314 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1348 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1350 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1373 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1375 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1457 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1476 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1593 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1828 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
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