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Searched refs:pin_mask (Results 1 - 25 of 29) sorted by relevance

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/kernel/linux/linux-5.10/arch/powerpc/sysdev/
H A Dcpm_common.c122 u32 pin_mask; in cpm2_gpio32_get() local
124 pin_mask = 1 << (31 - gpio); in cpm2_gpio32_get()
126 return !!(in_be32(&iop->dat) & pin_mask); in cpm2_gpio32_get()
129 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, in __cpm2_gpio32_set() argument
136 cpm2_gc->cpdata |= pin_mask; in __cpm2_gpio32_set()
138 cpm2_gc->cpdata &= ~pin_mask; in __cpm2_gpio32_set()
148 u32 pin_mask = 1 << (31 - gpio); in cpm2_gpio32_set() local
152 __cpm2_gpio32_set(mm_gc, pin_mask, value); in cpm2_gpio32_set()
163 u32 pin_mask = 1 << (31 - gpio); in cpm2_gpio32_dir_out() local
167 setbits32(&iop->dir, pin_mask); in cpm2_gpio32_dir_out()
181 u32 pin_mask = 1 << (31 - gpio); cpm2_gpio32_dir_in() local
[all...]
/kernel/linux/linux-6.6/arch/powerpc/sysdev/
H A Dcpm_common.c120 u32 pin_mask; in cpm2_gpio32_get() local
122 pin_mask = 1 << (31 - gpio); in cpm2_gpio32_get()
124 return !!(in_be32(&iop->dat) & pin_mask); in cpm2_gpio32_get()
127 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, in __cpm2_gpio32_set() argument
134 cpm2_gc->cpdata |= pin_mask; in __cpm2_gpio32_set()
136 cpm2_gc->cpdata &= ~pin_mask; in __cpm2_gpio32_set()
146 u32 pin_mask = 1 << (31 - gpio); in cpm2_gpio32_set() local
150 __cpm2_gpio32_set(mm_gc, pin_mask, value); in cpm2_gpio32_set()
161 u32 pin_mask = 1 << (31 - gpio); in cpm2_gpio32_dir_out() local
165 setbits32(&iop->dir, pin_mask); in cpm2_gpio32_dir_out()
179 u32 pin_mask = 1 << (31 - gpio); cpm2_gpio32_dir_in() local
[all...]
/kernel/linux/linux-5.10/arch/powerpc/platforms/8xx/
H A Dcpm1.c544 u16 pin_mask; in cpm1_gpio16_get() local
546 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_get()
548 return !!(in_be16(&iop->dat) & pin_mask); in cpm1_gpio16_get()
551 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, in __cpm1_gpio16_set() argument
558 cpm1_gc->cpdata |= pin_mask; in __cpm1_gpio16_set()
560 cpm1_gc->cpdata &= ~pin_mask; in __cpm1_gpio16_set()
570 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_set() local
574 __cpm1_gpio16_set(mm_gc, pin_mask, value); in cpm1_gpio16_set()
593 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_dir_out() local
597 setbits16(&iop->dir, pin_mask); in cpm1_gpio16_dir_out()
611 u16 pin_mask = 1 << (15 - gpio); cpm1_gpio16_dir_in() local
681 u32 pin_mask; cpm1_gpio32_get() local
688 __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, int value) __cpm1_gpio32_set() argument
707 u32 pin_mask = 1 << (31 - gpio); cpm1_gpio32_set() local
722 u32 pin_mask = 1 << (31 - gpio); cpm1_gpio32_dir_out() local
740 u32 pin_mask = 1 << (31 - gpio); cpm1_gpio32_dir_in() local
[all...]
/kernel/linux/linux-6.6/arch/powerpc/platforms/8xx/
H A Dcpm1.c401 u16 pin_mask; in cpm1_gpio16_get() local
403 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_get()
405 return !!(in_be16(&iop->dat) & pin_mask); in cpm1_gpio16_get()
408 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, in __cpm1_gpio16_set() argument
415 cpm1_gc->cpdata |= pin_mask; in __cpm1_gpio16_set()
417 cpm1_gc->cpdata &= ~pin_mask; in __cpm1_gpio16_set()
427 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_set() local
431 __cpm1_gpio16_set(mm_gc, pin_mask, value); in cpm1_gpio16_set()
450 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_dir_out() local
454 setbits16(&iop->dir, pin_mask); in cpm1_gpio16_dir_out()
468 u16 pin_mask = 1 << (15 - gpio); cpm1_gpio16_dir_in() local
538 u32 pin_mask; cpm1_gpio32_get() local
545 __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, int value) __cpm1_gpio32_set() argument
564 u32 pin_mask = 1 << (31 - gpio); cpm1_gpio32_set() local
579 u32 pin_mask = 1 << (31 - gpio); cpm1_gpio32_dir_out() local
597 u32 pin_mask = 1 << (31 - gpio); cpm1_gpio32_dir_in() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_hotplug_irq.c342 u32 *pin_mask, u32 *long_mask, in intel_get_hpd_pins()
349 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); in intel_get_hpd_pins()
355 *pin_mask |= BIT(pin); in intel_get_hpd_pins()
363 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); in intel_get_hpd_pins()
455 u32 pin_mask = 0, long_mask = 0; in i9xx_hpd_irq_handler() local
465 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
470 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
481 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; in ibx_hpd_irq_handler() local
502 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in ibx_hpd_irq_handler()
507 intel_hpd_irq_handler(dev_priv, pin_mask, long_mas in ibx_hpd_irq_handler()
341 intel_get_hpd_pins(struct drm_i915_private *dev_priv, u32 *pin_mask, u32 *long_mask, u32 hotplug_trigger, u32 dig_hotplug_reg, const u32 hpd[HPD_NUM_PINS], bool long_pulse_detect(enum hpd_pin pin, u32 val)) intel_get_hpd_pins() argument
515 u32 pin_mask = 0, long_mask = 0; xelpdp_pica_irq_handler() local
552 u32 pin_mask = 0, long_mask = 0; icp_irq_handler() local
591 u32 pin_mask = 0, long_mask = 0; spt_irq_handler() local
624 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; ilk_hpd_irq_handler() local
638 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; bxt_hpd_irq_handler() local
652 u32 pin_mask = 0, long_mask = 0; gen11_hpd_irq_handler() local
[all...]
H A Dintel_hotplug.h22 u32 pin_mask, u32 long_mask);
H A Dintel_hotplug.c473 * @pin_mask: a mask of hpd pins that have triggered the irq
479 * triggered (@pin_mask), and which of those pins may be long pulses
487 u32 pin_mask, u32 long_mask) in intel_hpd_irq_handler()
496 if (!pin_mask) in intel_hpd_irq_handler()
512 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
539 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
486 intel_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 pin_mask, u32 long_mask) intel_hpd_irq_handler() argument
H A Dintel_tc.c282 u32 pin_mask; in intel_tc_port_get_pin_assignment_mask() local
284 pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(tc->phy_fia)); in intel_tc_port_get_pin_assignment_mask()
286 drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff); in intel_tc_port_get_pin_assignment_mask()
289 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx)) >> in intel_tc_port_get_pin_assignment_mask()
297 u32 pin_mask; in mtl_tc_port_get_pin_assignment_mask() local
300 pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); in mtl_tc_port_get_pin_assignment_mask()
302 switch (pin_mask) { in mtl_tc_port_get_pin_assignment_mask()
304 MISSING_CASE(pin_mask); in mtl_tc_port_get_pin_assignment_mask()
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-mxs.c73 u32 pin_mask = 1 << d->hwirq; in mxs_gpio_set_irq_type() local
84 port->both_edges &= ~pin_mask; in mxs_gpio_set_irq_type()
87 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; in mxs_gpio_set_irq_type()
92 port->both_edges |= pin_mask; in mxs_gpio_set_irq_type()
113 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
114 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); in mxs_gpio_set_irq_type()
116 writel(pin_mask, pin_addr + MXS_CLR); in mxs_gpio_set_irq_type()
117 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); in mxs_gpio_set_irq_type()
123 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
125 writel(pin_mask, pin_add in mxs_gpio_set_irq_type()
[all...]
H A Dgpio-tegra.c209 u32 pin_mask = BIT(GPIO_BIT(offset)); in tegra_gpio_get_direction() local
213 if (!(cnf & pin_mask)) in tegra_gpio_get_direction()
218 if (oe & pin_mask) in tegra_gpio_get_direction()
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-mxs.c67 u32 pin_mask = 1 << d->hwirq; in mxs_gpio_set_irq_type() local
78 port->both_edges &= ~pin_mask; in mxs_gpio_set_irq_type()
81 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; in mxs_gpio_set_irq_type()
86 port->both_edges |= pin_mask; in mxs_gpio_set_irq_type()
107 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
108 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); in mxs_gpio_set_irq_type()
110 writel(pin_mask, pin_addr + MXS_CLR); in mxs_gpio_set_irq_type()
111 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); in mxs_gpio_set_irq_type()
117 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
119 writel(pin_mask, pin_add in mxs_gpio_set_irq_type()
[all...]
H A Dgpio-aspeed-sgpio.c28 const u32 pin_mask; member
483 .pin_mask = GENMASK(9, 6),
525 .pin_mask = GENMASK(10, 6),
539 u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask; in aspeed_sgpio_probe() local
559 pin_mask = pdata->pin_mask; in aspeed_sgpio_probe()
602 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask; in aspeed_sgpio_probe()
H A Dgpio-tegra.c215 u32 pin_mask = BIT(GPIO_BIT(offset)); in tegra_gpio_get_direction() local
219 if (!(cnf & pin_mask)) in tegra_gpio_get_direction()
224 if (oe & pin_mask) in tegra_gpio_get_direction()
/kernel/linux/linux-5.10/drivers/soc/fsl/qe/
H A Dqe_io.c122 u32 pin_mask, tmp_val; in par_io_data_set() local
129 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); in par_io_data_set()
134 qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata); in par_io_data_set()
136 qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata); in par_io_data_set()
H A Dgpio.c57 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get() local
59 return !!(qe_ioread32be(&regs->cpdata) & pin_mask); in qe_gpio_get()
68 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set() local
73 qe_gc->cpdata |= pin_mask; in qe_gpio_set()
75 qe_gc->cpdata &= ~pin_mask; in qe_gpio_set()
/kernel/linux/linux-6.6/drivers/soc/fsl/qe/
H A Dqe_io.c122 u32 pin_mask, tmp_val; in par_io_data_set() local
129 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); in par_io_data_set()
134 iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata); in par_io_data_set()
136 iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata); in par_io_data_set()
H A Dgpio.c55 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get() local
57 return !!(ioread32be(&regs->cpdata) & pin_mask); in qe_gpio_get()
66 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set() local
71 qe_gc->cpdata |= pin_mask; in qe_gpio_set()
73 qe_gc->cpdata &= ~pin_mask; in qe_gpio_set()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_irq.c1170 u32 *pin_mask, u32 *long_mask, in intel_get_hpd_pins()
1177 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); in intel_get_hpd_pins()
1183 *pin_mask |= BIT(pin); in intel_get_hpd_pins()
1191 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); in intel_get_hpd_pins()
1498 u32 pin_mask = 0, long_mask = 0; in i9xx_hpd_irq_handler() local
1508 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
1513 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
1687 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; in ibx_hpd_irq_handler() local
1708 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in ibx_hpd_irq_handler()
1713 intel_hpd_irq_handler(dev_priv, pin_mask, long_mas in ibx_hpd_irq_handler()
1169 intel_get_hpd_pins(struct drm_i915_private *dev_priv, u32 *pin_mask, u32 *long_mask, u32 hotplug_trigger, u32 dig_hotplug_reg, const u32 hpd[HPD_NUM_PINS], bool long_pulse_detect(enum hpd_pin pin, u32 val)) intel_get_hpd_pins() argument
1844 u32 pin_mask = 0, long_mask = 0; icp_irq_handler() local
1900 u32 pin_mask = 0, long_mask = 0; spt_irq_handler() local
1936 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; ilk_hpd_irq_handler() local
2115 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; bxt_hpd_irq_handler() local
2130 u32 pin_mask = 0, long_mask = 0; gen11_hpd_irq_handler() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H A Dtvnv17.c130 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) in get_tv_detect_quirks() argument
136 *pin_mask = device->quirk->tv_pin_mask; in get_tv_detect_quirks()
151 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); in nv17_tv_detect()
159 tv_enc->pin_mask = in nv17_tv_detect()
162 tv_enc->pin_mask = in nv17_tv_detect()
166 switch (tv_enc->pin_mask) { in nv17_tv_detect()
804 tv_enc->pin_mask = 0; in nv17_tv_create()
H A Dtvnv17.h83 uint32_t pin_mask; member
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
H A Dtvnv17.c131 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) in get_tv_detect_quirks() argument
137 *pin_mask = device->quirk->tv_pin_mask; in get_tv_detect_quirks()
152 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); in nv17_tv_detect()
160 tv_enc->pin_mask = in nv17_tv_detect()
163 tv_enc->pin_mask = in nv17_tv_detect()
167 switch (tv_enc->pin_mask) { in nv17_tv_detect()
805 tv_enc->pin_mask = 0; in nv17_tv_create()
H A Dtvnv17.h83 uint32_t pin_mask; member
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_hotplug.c450 * @pin_mask: a mask of hpd pins that have triggered the irq
456 * triggered (@pin_mask), and which of those pins may be long pulses
464 u32 pin_mask, u32 long_mask) in intel_hpd_irq_handler()
473 if (!pin_mask) in intel_hpd_irq_handler()
489 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
516 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
463 intel_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 pin_mask, u32 long_mask) intel_hpd_irq_handler() argument
H A Dintel_hotplug.h21 u32 pin_mask, u32 long_mask);
H A Dintel_tc.c102 u32 pin_mask; in intel_tc_port_get_pin_assignment_mask() local
104 pin_mask = intel_uncore_read(uncore, in intel_tc_port_get_pin_assignment_mask()
107 drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff); in intel_tc_port_get_pin_assignment_mask()
110 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >> in intel_tc_port_get_pin_assignment_mask()

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