pending_flush_mask (reference) in projects: kernel - OpenGrok search results

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Searched refs:pending_flush_mask (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A D	dpu_hw_ctl.c	81 trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_start() 93 trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_pending() 100 trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, in dpu_hw_ctl_clear_pending_flush() 102 ctx->pending_flush_mask = 0x0; in dpu_hw_ctl_clear_pending_flush() 116 ctx->pending_flush_mask); in dpu_hw_ctl_update_pending_flush() 117 ctx->pending_flush_mask \|= flushbits; in dpu_hw_ctl_update_pending_flush() 122 return ctx->pending_flush_mask; in dpu_hw_ctl_get_pending_flush() 129 if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) in dpu_hw_ctl_trigger_flush_v1() 132 if (ctx->pending_flush_mask & BIT(INTF_IDX)) in dpu_hw_ctl_trigger_flush_v1() 135 if (ctx->pending_flush_mask in dpu_hw_ctl_trigger_flush_v1() [all...]
H A D	dpu_hw_ctl.h	83 * Clear the value of the cached pending_flush_mask 90 * Query the value of the cached pending_flush_mask 97 * OR in the given flushbits to the cached pending_flush_mask 133 * OR in the given flushbits to the cached pending_flush_mask 142 * OR in the given flushbits to the cached pending_flush_mask 151 * OR in the given flushbits to the cached pending_flush_mask 170 * Write the value of the pending_flush_mask to hardware 238 * @pending_flush_mask: storage for pending ctl_flush managed via ops 253 u32 pending_flush_mask; member
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A D	dpu_hw_ctl.c	80 trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_start() 87 trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_pending() 94 trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, in dpu_hw_ctl_clear_pending_flush() 96 ctx->pending_flush_mask = 0x0; in dpu_hw_ctl_clear_pending_flush() 103 ctx->pending_flush_mask); in dpu_hw_ctl_update_pending_flush() 104 ctx->pending_flush_mask \|= flushbits; in dpu_hw_ctl_update_pending_flush() 115 return ctx->pending_flush_mask; in dpu_hw_ctl_get_pending_flush() 121 if (ctx->pending_flush_mask & BIT(INTF_IDX)) in dpu_hw_ctl_trigger_flush_v1() 125 DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); in dpu_hw_ctl_trigger_flush_v1() 130 trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_flush() [all...]
H A D	dpu_hw_ctl.h	`71 * Clear the value of the cached pending_flush_mask 78 * Query the value of the cached pending_flush_mask 85 * OR in the given flushbits to the cached pending_flush_mask 103 * Write the value of the pending_flush_mask to hardware 186 * @pending_flush_mask: storage for pending ctl_flush managed via ops 199 u32 pending_flush_mask; member`

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