Searched refs:pd_bit (Results 1 - 4 of 4) sorted by relevance
| /kernel/linux/linux-5.10/drivers/clk/zte/ |
| H A D | clk.c | 53 /* Check availability of pd_bit */ in hw_to_idx()
54 if (zx_pll->pd_bit < 32) in hw_to_idx()
55 hw_cfg0 |= BIT(zx_pll->pd_bit); in hw_to_idx()
111 /* If pd_bit is not available, simply return success. */ in zx_pll_enable()
112 if (zx_pll->pd_bit > 31) in zx_pll_enable()
116 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_enable()
127 if (zx_pll->pd_bit > 31) in zx_pll_disable()
131 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_disable()
141 return !(reg & BIT(zx_pll->pd_bit)); in zx_pll_is_enabled()
177 zx_pll->pd_bit in clk_register_zx_pll()
[all...] |
| H A D | clk.h | 26 u8 pd_bit; /* power down bit */ member
42 .pd_bit = _pd, \
49 * The pd_bit is not available on ZX296718, so let's pass something
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| /kernel/linux/linux-6.6/drivers/clk/ |
| H A D | clk-sp7021.c | 54 int pd_bit; /* power down bit idx */ member
515 writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); in sp_pll_enable()
524 writel(BIT(clk->pd_bit + 16), clk->reg); in sp_pll_disable()
531 return readl(clk->reg) & BIT(clk->pd_bit); in sp_pll_is_enabled()
552 void __iomem *reg, int pd_bit, int bp_bit, in sp_pll_register()
573 pll->pd_bit = pd_bit; in sp_pll_register()
550 sp_pll_register(struct device *dev, const char *name, const struct clk_parent_data *parent_data, void __iomem *reg, int pd_bit, int bp_bit, unsigned long brate, int shift, int width, unsigned long flags) sp_pll_register() argument
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| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| H A D | pinctrl-ocelot.c | 319 u8 pd_bit; member
1353 *val = regcfg & (opd->pd_bit | opd->pu_bit); in ocelot_hw_get_value()
1408 opd->pd_bit | opd->pu_bit, in ocelot_hw_set_value()
1452 val = !!(val & info->pincfg_data->pd_bit); in ocelot_pinconf_get()
1523 opd->pu_bit : opd->pd_bit; in ocelot_pinconf_set()
1662 .pd_bit = BIT(4),
1680 .pd_bit = BIT(3),
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