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Searched refs:ocsc_mode (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c136 enum mpc_output_csc_mode ocsc_mode) in mpc2_set_output_csc()
142 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) { in mpc2_set_output_csc()
143 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
161 ocsc_mode = MPC_OUTPUT_CSC_COEF_A; in mpc2_set_output_csc()
163 ocsc_mode = MPC_OUTPUT_CSC_COEF_B; in mpc2_set_output_csc()
170 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { in mpc2_set_output_csc()
183 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
190 enum mpc_output_csc_mode ocsc_mode) in mpc2_set_ocsc_default()
198 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) { in mpc2_set_ocsc_default()
199 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
132 mpc2_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc2_set_output_csc() argument
186 mpc2_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc2_set_ocsc_default() argument
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H A Ddcn20_mpc.h296 enum mpc_output_csc_mode ocsc_mode);
302 enum mpc_output_csc_mode ocsc_mode);
H A Ddcn20_hwseq.c778 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; in dcn20_program_output_csc() local
789 ocsc_mode); in dcn20_program_output_csc()
795 ocsc_mode); in dcn20_program_output_csc()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c135 enum mpc_output_csc_mode ocsc_mode) in mpc2_set_output_csc()
141 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) { in mpc2_set_output_csc()
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
160 ocsc_mode = MPC_OUTPUT_CSC_COEF_A; in mpc2_set_output_csc()
162 ocsc_mode = MPC_OUTPUT_CSC_COEF_B; in mpc2_set_output_csc()
169 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { in mpc2_set_output_csc()
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
189 enum mpc_output_csc_mode ocsc_mode) in mpc2_set_ocsc_default()
197 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) { in mpc2_set_ocsc_default()
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
131 mpc2_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc2_set_output_csc() argument
185 mpc2_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc2_set_ocsc_default() argument
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H A Ddcn20_mpc.h296 enum mpc_output_csc_mode ocsc_mode);
302 enum mpc_output_csc_mode ocsc_mode);
H A Ddcn20_hwseq.c828 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; in dcn20_program_output_csc() local
839 ocsc_mode); in dcn20_program_output_csc()
845 ocsc_mode); in dcn20_program_output_csc()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c577 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A; in hwss_build_fast_sequence()
584 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A; in hwss_build_fast_sequence()
769 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode; in hwss_set_output_csc() local
775 ocsc_mode); in hwss_set_output_csc()
783 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode; in hwss_set_ocsc_default() local
789 ocsc_mode); in hwss_set_ocsc_default()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h318 enum mpc_output_csc_mode ocsc_mode);
323 enum mpc_output_csc_mode ocsc_mode);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h372 enum mpc_output_csc_mode ocsc_mode);
377 enum mpc_output_csc_mode ocsc_mode);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c188 uint32_t ocsc_mode; in dpp1_cm_program_color_matrix() local
208 ocsc_mode = 4; in dpp1_cm_program_color_matrix()
210 ocsc_mode = 5; in dpp1_cm_program_color_matrix()
218 if (ocsc_mode == 4) { in dpp1_cm_program_color_matrix()
235 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c188 uint32_t ocsc_mode; in dpp1_cm_program_color_matrix() local
208 ocsc_mode = 4; in dpp1_cm_program_color_matrix()
210 ocsc_mode = 5; in dpp1_cm_program_color_matrix()
218 if (ocsc_mode == 4) { in dpp1_cm_program_color_matrix()
235 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c1206 enum mpc_output_csc_mode ocsc_mode) in mpc3_set_output_csc()
1213 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc3_set_output_csc()
1215 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) in mpc3_set_output_csc()
1228 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { in mpc3_set_output_csc()
1245 enum mpc_output_csc_mode ocsc_mode) in mpc3_set_ocsc_default()
1254 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc3_set_ocsc_default()
1255 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) in mpc3_set_ocsc_default()
1271 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { in mpc3_set_ocsc_default()
1202 mpc3_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc3_set_output_csc() argument
1241 mpc3_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc3_set_ocsc_default() argument
H A Ddcn30_mpc.h638 enum mpc_output_csc_mode ocsc_mode);
644 enum mpc_output_csc_mode ocsc_mode);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c1238 enum mpc_output_csc_mode ocsc_mode) in mpc3_set_output_csc()
1245 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc3_set_output_csc()
1247 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) in mpc3_set_output_csc()
1260 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { in mpc3_set_output_csc()
1277 enum mpc_output_csc_mode ocsc_mode) in mpc3_set_ocsc_default()
1286 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc3_set_ocsc_default()
1287 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) in mpc3_set_ocsc_default()
1303 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { in mpc3_set_ocsc_default()
1234 mpc3_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc3_set_output_csc() argument
1273 mpc3_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc3_set_ocsc_default() argument
H A Ddcn30_mpc.h1038 enum mpc_output_csc_mode ocsc_mode);
1044 enum mpc_output_csc_mode ocsc_mode);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/
H A Dhw_sequencer.h127 enum mpc_output_csc_mode ocsc_mode; member
134 enum mpc_output_csc_mode ocsc_mode; member

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