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Searched refs:num_states (Results 1 - 25 of 74) sorted by relevance

123

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c125 .num_states = 1,
194 unsigned int num_states = 0; in dcn303_fpu_update_bw_bounding_box() local
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
279 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
283 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
293 dram_speed_mts[num_states in dcn303_fpu_update_bw_bounding_box()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c126 .num_states = 1,
198 unsigned int num_states = 0; in dcn302_fpu_update_bw_bounding_box() local
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states in dcn302_fpu_update_bw_bounding_box()
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/kernel/linux/linux-5.10/arch/powerpc/kernel/
H A Drtas-proc.c513 int num_states = 0; in ppc_rtas_process_sensor() local
522 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
523 if (state < num_states) { in ppc_rtas_process_sensor()
530 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
531 if (state < num_states) { in ppc_rtas_process_sensor()
543 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
544 if (state < num_states) { in ppc_rtas_process_sensor()
551 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
552 if (state < num_states) { in ppc_rtas_process_sensor()
563 num_states in ppc_rtas_process_sensor()
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/kernel/linux/linux-6.6/arch/powerpc/kernel/
H A Drtas-proc.c508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states in ppc_rtas_process_sensor()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c122 .num_states = 1,
696 unsigned int i = 0, j = 0, num_states = 0; in dcn321_update_bw_bounding_box_fpu() local
767 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
769 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
770 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
773 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
774 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
781 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
782 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
783 dram_speed_mts[num_states in dcn321_update_bw_bounding_box_fpu()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
343 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
368 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
370 s[dcn3_01_soc.num_states] = in dcn301_update_bw_bounding_box()
371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_update_bw_bounding_box()
372 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/regulator/
H A Dirq_helpers.c62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
427 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1)) in regulator_irq_map_event_simple()
/kernel/linux/linux-5.10/net/netfilter/ipvs/
H A Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
/kernel/linux/linux-6.6/net/netfilter/ipvs/
H A Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c169 .num_states = 5,
412 .num_states = 5,
609 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
641 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
702 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
748 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
758 closest_clk_lvl = dcn3_16_soc.num_states - 1; in dcn316_update_bw_bounding_box()
793 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1673 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1695 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1862 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2076 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2092 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2174 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2176 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2177 dram_speed_mts[num_states in dcn30_update_bw_bounding_box()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c182 .num_states = 1,
1802 dcn3_0_soc.num_states = in init_soc_bounding_box()
1803 le32_to_cpu(bb->num_states); in init_soc_bounding_box()
1805 for (i = 0; i < dcn3_0_soc.num_states; i++) { in init_soc_bounding_box()
1982 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1985 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1998 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
2021 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2186 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2424 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2462 unsigned int num_states = 0; dcn30_update_bw_bounding_box() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c133 .num_states = 1,
287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
428 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) in dcn32_predict_pipe_split()
1177 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1191 (*vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_full_validate_bw_helper()
1210 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. in dcn32_full_validate_bw_helper()
1217 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1241 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; in dcn32_full_validate_bw_helper()
2785 unsigned int i = 0, j = 0, num_states = 0; dcn32_update_bw_bounding_box_fpu() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c150 .num_states = 5,
217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { in dcn314_update_bw_bounding_box_fpu()
225 closest_clk_lvl = dcn3_14_soc.num_states - 1; in dcn314_update_bw_bounding_box_fpu()
259 dcn3_14_soc.num_states = clk_table->num_entries; in dcn314_update_bw_bounding_box_fpu()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c289 .num_states = 5,
400 .num_states = 5,
511 .num_states = 5,
762 .num_states = 8
1843 unsigned int num_states) in dcn20_update_bounding_box()
1851 if (num_states == 0) in dcn20_update_bounding_box()
1867 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1898 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1902 bb->clock_limits[num_calculated_states].state = bb->num_states; in dcn20_update_bounding_box()
1913 for (i = 0; i < bb->num_states; in dcn20_cap_soc_clocks()
1839 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) dcn20_update_bounding_box() argument
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H A Ddcn20_fpu.h61 unsigned int num_states);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c299 .num_states = 5,
410 .num_states = 5,
2715 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2720 if (vlevel > context->bw_ctx.dml.soc.num_states)
2867 if (vlevel > context->bw_ctx.dml.soc.num_states)
2938 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
3177 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3426 for (i = 0; i < bb->num_states; i++) {
3461 for (i = bb->num_states - 1; i > 1; i--) {
3482 bb->num_states
3486 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) global() argument
3737 unsigned int num_states = 0; global() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c304 .num_states = 8
1035 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1214 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn21_validate_bandwidth_fp()
1420 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { in update_bw_bounding_box()
1444 dcn2_1_soc.num_states = clk_table->num_entries; in update_bw_bounding_box()
1446 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; in update_bw_bounding_box()
1447 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; in update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1901 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2050 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2123 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2344 unsigned int num_states = 0; in init_soc_bounding_box() local
2351 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2366 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2368 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2566 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2574 } else if (loaded_bb->num_states > in dcn20_resource_construct()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c2059 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3955 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3964 if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3965 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3970 if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3971 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3976 if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3977 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
4085 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states in dml30_ModeSupportAndSystemConfigurationFull()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c1990 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3854 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3863 if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3864 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3869 if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3870 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3875 if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3876 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3984 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states in dml30_ModeSupportAndSystemConfigurationFull()
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