Home
last modified time | relevance | path

Searched refs:msr_base (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/tools/testing/selftests/kvm/x86_64/
H A Dpmu_event_filter_test.c147 static void run_and_measure_loop(uint32_t msr_base) in run_and_measure_loop() argument
149 const uint64_t branches_retired = rdmsr(msr_base + 0); in run_and_measure_loop()
150 const uint64_t insn_retired = rdmsr(msr_base + 1); in run_and_measure_loop()
154 pmc_results.branches_retired = rdmsr(msr_base + 0) - branches_retired; in run_and_measure_loop()
155 pmc_results.instructions_retired = rdmsr(msr_base + 1) - insn_retired; in run_and_measure_loop()
498 static void masked_events_guest_test(uint32_t msr_base) in masked_events_guest_test() argument
504 const uint64_t loads = rdmsr(msr_base + 0); in masked_events_guest_test()
505 const uint64_t stores = rdmsr(msr_base + 1); in masked_events_guest_test()
506 const uint64_t loads_stores = rdmsr(msr_base + 2); in masked_events_guest_test()
515 pmc_results.loads = rdmsr(msr_base in masked_events_guest_test()
[all...]
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/resctrl/
H A Dcore.c68 .msr_base = MSR_IA32_L3_CBM_BASE,
85 .msr_base = MSR_IA32_L3_CBM_BASE,
102 .msr_base = MSR_IA32_L3_CBM_BASE,
119 .msr_base = MSR_IA32_L2_CBM_BASE,
136 .msr_base = MSR_IA32_L2_CBM_BASE,
153 .msr_base = MSR_IA32_L2_CBM_BASE,
370 wrmsrl(r->msr_base + i, d->ctrl_val[i]); in mba_wrmsr_amd()
395 wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r)); in mba_wrmsr_intel()
404 wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]); in cat_wrmsr()
932 r->msr_base in rdt_init_res_defs_intel()
[all...]
H A Dinternal.h454 * @msr_base: Base MSR address for CBMs
476 unsigned int msr_base; member
H A Dmonitor.c418 cur_msr = r_mba->msr_base + closid; in update_mba_bw()
/kernel/linux/linux-5.10/arch/x86/events/amd/
H A Duncore.c46 u32 msr_base; member
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
382 uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL; in amd_uncore_cpu_up_prepare()
396 uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL; in amd_uncore_cpu_up_prepare()
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/resctrl/
H A Dcore.c74 .msr_base = MSR_IA32_L3_CBM_BASE,
88 .msr_base = MSR_IA32_L2_CBM_BASE,
308 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); in mba_wrmsr_amd()
335 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r)); in mba_wrmsr_intel()
346 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); in cat_wrmsr()
877 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; in rdt_init_res_defs_intel()
897 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; in rdt_init_res_defs_amd()
900 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; in rdt_init_res_defs_amd()
H A Dinternal.h389 * @msr_base: Base MSR address for CBMs
399 * msr_update and msr_base.
404 unsigned int msr_base; member
/kernel/linux/linux-6.6/arch/x86/events/amd/
H A Duncore.c46 u32 msr_base; member
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
453 uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL; in amd_uncore_cpu_up_prepare()
471 uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL; in amd_uncore_cpu_up_prepare()

Completed in 10 milliseconds