| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_mpc.c | 42 int mpcc_id) in mpc1_set_bg_color()
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
61 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
63 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
65 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 int mpcc_id) in mpc1_update_blending()
75 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending()
77 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], in mpc1_update_blending()
84 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); in mpc1_update_blending()
91 int mpcc_id) in mpc1_update_stereo_mix()
40 mpc1_set_bg_color(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id) mpc1_set_bg_color() argument
69 mpc1_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) mpc1_update_blending() argument
88 mpc1_update_stereo_mix( struct mpc *mpc, struct mpcc_sm_cfg *sm_cfg, int mpcc_id) mpc1_update_stereo_mix() argument
113 mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) mpc1_get_mpcc() argument
139 mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) mpc1_is_mpcc_idle() argument
155 mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) mpc1_assert_mpcc_idle_before_connect() argument
189 mpc1_insert_plane( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id) mpc1_insert_plane() argument
288 int mpcc_id = mpcc_to_remove->mpcc_id; mpc1_remove_mpcc() local
368 int mpcc_id; mpc1_mpc_init() local
387 mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) mpc1_mpc_init_single_inst() argument
416 int mpcc_id; mpc1_init_mpcc_list_from_hw() local
[all...] |
| H A D | dcn10_mpc.h | 148 int mpcc_id);
160 unsigned int mpcc_id);
174 int mpcc_id);
178 int mpcc_id);
182 int mpcc_id);
190 int mpcc_id);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_mpc.c | 42 int mpcc_id) in mpc1_set_bg_color()
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
79 int mpcc_id) in mpc1_update_blending()
82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending()
84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], in mpc1_update_blending()
97 int mpcc_id) in mpc1_update_stereo_mix()
101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], in mpc1_update_stereo_mix()
40 mpc1_set_bg_color(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id) mpc1_set_bg_color() argument
76 mpc1_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) mpc1_update_blending() argument
94 mpc1_update_stereo_mix( struct mpc *mpc, struct mpcc_sm_cfg *sm_cfg, int mpcc_id) mpc1_update_stereo_mix() argument
119 mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) mpc1_get_mpcc() argument
145 mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) mpc1_is_mpcc_idle() argument
161 mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) mpc1_assert_mpcc_idle_before_connect() argument
195 mpc1_insert_plane( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id) mpc1_insert_plane() argument
294 int mpcc_id = mpcc_to_remove->mpcc_id; mpc1_remove_mpcc() local
374 int mpcc_id; mpc1_mpc_init() local
393 mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) mpc1_mpc_init_single_inst() argument
422 int mpcc_id; mpc1_init_mpcc_list_from_hw() local
[all...] |
| H A D | dcn10_mpc.h | 148 int mpcc_id);
160 unsigned int mpcc_id);
174 int mpcc_id);
178 int mpcc_id);
182 int mpcc_id);
190 int mpcc_id);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_mpc.c | 48 int mpcc_id; in mpc32_mpc_init() local
54 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { in mpc32_mpc_init()
55 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
61 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id in mpc32_mpc_init()
67 mpc32_power_on_blnd_lut( struct mpc *mpc, uint32_t mpcc_id, bool power_on) mpc32_power_on_blnd_lut() argument
91 mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id) mpc32_get_post1dlut_current() argument
123 mpc32_configure_post1dlut( struct mpc *mpc, uint32_t mpcc_id, bool is_ram_a) mpc32_configure_post1dlut() argument
166 mpc32_program_post1dluta_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) mpc32_program_post1dluta_settings() argument
195 mpc32_program_post1dlutb_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) mpc32_program_post1dlutb_settings() argument
223 mpc32_program_post1dlut_pwl( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_result_data *rgb, uint32_t num) mpc32_program_post1dlut_pwl() argument
257 mpc32_program_post1dlut( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) mpc32_program_post1dlut() argument
297 mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id) mpc32_get_shaper_current() argument
324 mpc32_configure_shaper_lut( struct mpc *mpc, bool is_ram_a, uint32_t mpcc_id) mpc32_configure_shaper_lut() argument
339 mpc32_program_shaper_luta_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) mpc32_program_shaper_luta_settings() argument
489 mpc32_program_shaper_lutb_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) mpc32_program_shaper_lutb_settings() argument
640 mpc32_program_shaper_lut( struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num, uint32_t mpcc_id) mpc32_program_shaper_lut() argument
674 mpc32_power_on_shaper_3dlut( struct mpc *mpc, uint32_t mpcc_id, bool power_on) mpc32_power_on_shaper_3dlut() argument
704 mpc32_program_shaper( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) mpc32_program_shaper() argument
746 get3dlut_config( struct mpc *mpc, bool *is_17x17x17, bool *is_12bits_color_channel, int mpcc_id) get3dlut_config() argument
792 mpc32_select_3dlut_ram( struct mpc *mpc, enum dc_lut_mode mode, bool is_color_channel_12bits, uint32_t mpcc_id) mpc32_select_3dlut_ram() argument
806 mpc32_select_3dlut_ram_mask( struct mpc *mpc, uint32_t ram_selection_mask, uint32_t mpcc_id) mpc32_select_3dlut_ram_mask() argument
819 mpc32_set3dlut_ram12( struct mpc *mpc, const struct dc_rgb *lut, uint32_t entries, uint32_t mpcc_id) mpc32_set3dlut_ram12() argument
851 mpc32_set3dlut_ram10( struct mpc *mpc, const struct dc_rgb *lut, uint32_t entries, uint32_t mpcc_id) mpc32_set3dlut_ram10() argument
873 mpc32_set_3dlut_mode( struct mpc *mpc, enum dc_lut_mode mode, bool is_color_channel_12bits, bool is_lut_size17x17x17, uint32_t mpcc_id) mpc32_set_3dlut_mode() argument
900 mpc32_program_3dlut( struct mpc *mpc, const struct tetrahedral_params *params, int mpcc_id) mpc32_program_3dlut() argument
[all...] |
| H A D | dcn32_mpc.h | 317 int mpcc_id);
321 uint32_t mpcc_id);
325 uint32_t mpcc_id);
337 uint32_t mpcc_id,
341 uint32_t mpcc_id,
346 uint32_t mpcc_id,
350 uint32_t mpcc_id,
354 uint32_t mpcc_id,
360 uint32_t mpcc_id);
364 uint32_t mpcc_id);
[all...] |
| H A D | dcn32_hwseq.c | 443 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut() local
465 mpcc_id); in dcn32_set_mpc_shaper_3dlut()
469 mpcc_id); in dcn32_set_mpc_shaper_3dlut()
479 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts() local
494 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
509 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
513 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); in dcn32_set_mcm_luts()
515 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); in dcn32_set_mcm_luts()
566 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func() local
590 mpc->funcs->set_output_gamma(mpc, mpcc_id, param in dcn32_set_output_transfer_func()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_mpc.c | 51 int mpcc_id) in mpc2_update_blending()
55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending()
57 REG_UPDATE_7(MPCC_CONTROL[mpcc_id], in mpc2_update_blending()
66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
70 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); in mpc2_update_blending()
274 struct mpc *mpc, int mpcc_id, in mpc20_power_on_ogam_lut()
279 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
285 struct mpc *mpc, int mpcc_id, in mpc20_configure_ogam_lut()
48 mpc2_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) mpc2_update_blending() argument
273 mpc20_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) mpc20_power_on_ogam_lut() argument
284 mpc20_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) mpc20_configure_ogam_lut() argument
297 mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id) mpc20_get_ogam_current() argument
323 mpc2_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc2_program_lutb() argument
350 mpc2_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc2_program_luta() argument
377 mpc20_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) mpc20_program_ogam_pwl() argument
404 apply_DEDCN20_305_wa( struct mpc *mpc, int mpcc_id, enum dc_lut_mode current_mode, enum dc_lut_mode next_mode) apply_DEDCN20_305_wa() argument
429 mpc2_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc2_set_output_gamma() argument
485 mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) mpc2_assert_mpcc_idle_before_connect() argument
[all...] |
| H A D | dcn20_mpc.h | 280 int mpcc_id);
306 int mpcc_id,
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
|
| H A D | dcn20_hwseq.c | 779 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_program_output_csc() local
782 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_program_output_csc()
802 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_set_output_transfer_func() local
813 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_set_output_transfer_func()
833 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn20_set_output_transfer_func()
1492 int mpcc_id = hubp->inst; in dcn20_update_dchubp_dpp() local
1516 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust); in dcn20_update_dchubp_dpp()
2257 int mpcc_id; in dcn20_update_mpcc() local
2311 mpcc_id = hubp->inst; in dcn20_update_mpcc()
2316 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn20_update_mpcc()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_mpc.c | 51 int mpcc_id) in mpc2_update_blending()
55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending()
57 REG_UPDATE_7(MPCC_CONTROL[mpcc_id], in mpc2_update_blending()
66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
273 struct mpc *mpc, int mpcc_id, in mpc20_power_on_ogam_lut()
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
284 struct mpc *mpc, int mpcc_id, in mpc20_configure_ogam_lut()
289 REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], in mpc20_configure_ogam_lut()
48 mpc2_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) mpc2_update_blending() argument
272 mpc20_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) mpc20_power_on_ogam_lut() argument
283 mpc20_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) mpc20_configure_ogam_lut() argument
296 mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id) mpc20_get_ogam_current() argument
322 mpc2_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc2_program_lutb() argument
349 mpc2_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc2_program_luta() argument
376 mpc20_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) mpc20_program_ogam_pwl() argument
403 apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id, enum dc_lut_mode current_mode, enum dc_lut_mode next_mode) apply_DEDCN20_305_wa() argument
427 mpc2_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc2_set_output_gamma() argument
483 mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) mpc2_assert_mpcc_idle_before_connect() argument
[all...] |
| H A D | dcn20_mpc.h | 280 int mpcc_id);
306 int mpcc_id,
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
|
| H A D | dcn20_hwseq.c | 829 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_program_output_csc() local
832 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_program_output_csc()
852 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_set_output_transfer_func() local
863 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_set_output_transfer_func()
883 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn20_set_output_transfer_func()
2594 int mpcc_id; in dcn20_update_mpcc() local
2638 mpcc_id = hubp->inst; in dcn20_update_mpcc()
2643 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn20_update_mpcc()
2644 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn20_update_mpcc()
2649 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); in dcn20_update_mpcc()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mpc.c | 65 int mpcc_id) in mpc3_set_dwb_mux()
70 MPC_DWB0_MUX, mpcc_id); in mpc3_set_dwb_mux()
102 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) in mpc3_get_ogam_current() argument
112 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode, in mpc3_get_ogam_current()
141 struct mpc *mpc, int mpcc_id, in mpc3_power_on_ogam_lut()
152 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], in mpc3_power_on_ogam_lut()
157 REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10); in mpc3_power_on_ogam_lut()
161 struct mpc *mpc, int mpcc_id, in mpc3_configure_ogam_lut()
166 REG_UPDATE_2(MPCC_OGAM_LUT_CONTROL[mpcc_id], in mpc3_configure_ogam_lut()
170 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], in mpc3_configure_ogam_lut()
62 mpc3_set_dwb_mux( struct mpc *mpc, int dwb_id, int mpcc_id) mpc3_set_dwb_mux() argument
140 mpc3_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) mpc3_power_on_ogam_lut() argument
160 mpc3_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) mpc3_configure_ogam_lut() argument
207 mpc3_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc3_program_luta() argument
240 mpc3_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc3_program_lutb() argument
274 mpc3_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) mpc3_program_ogam_pwl() argument
330 mpc3_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc3_set_output_gamma() argument
1055 program_gamut_remap( struct dcn30_mpc *mpc30, int mpcc_id, const uint16_t *regval, int select) program_gamut_remap() argument
1114 mpc3_set_gamut_remap( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust) mpc3_set_gamut_remap() argument
1346 mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx) mpcc3_acquire_rmu() argument
1365 mpcc3_release_rmu(struct mpc *mpc, int mpcc_id) mpcc3_release_rmu() argument
1387 int mpcc_id; mpc3_set_mpc_mem_lp_mode() local
[all...] |
| H A D | dcn30_resource.h | 86 int mpcc_id,
|
| H A D | dcn30_hwseq.c | 97 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut() local
124 if (mpcc_id_projected != mpcc_id) in dcn30_set_mpc_shaper_3dlut()
127 * mpcc_id into acquire_post_bldn_3dlut in dcn30_set_mpc_shaper_3dlut()
129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
139 // loop through the available mux and release the requested mpcc_id in dcn30_set_mpc_shaper_3dlut()
140 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func() local
217 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn30_set_output_transfer_func()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | mpc.h | 147 * @mpcc_id: MPCC physical instance
157 int mpcc_id; /* MPCC physical instance */ member
221 * [in] mpcc_id - The MPCC physical instance to use for blending.
232 int mpcc_id);
264 unsigned int mpcc_id);
274 * [in] mpcc_id - The MPCC physical instance.
281 int mpcc_id);
315 * [in] mpcc_id - The MPCC physical instance to use for blending.
326 int mpcc_id);
354 void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mpc.c | 65 int mpcc_id) in mpc3_set_dwb_mux()
70 MPC_DWB0_MUX, mpcc_id); in mpc3_set_dwb_mux()
102 static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) in mpc3_get_ogam_current() argument
112 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], in mpc3_get_ogam_current()
141 struct mpc *mpc, int mpcc_id, in mpc3_power_on_ogam_lut()
146 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc3_power_on_ogam_lut()
151 struct mpc *mpc, int mpcc_id, in mpc3_configure_ogam_lut()
156 REG_UPDATE_2(MPCC_OGAM_LUT_CONTROL[mpcc_id], in mpc3_configure_ogam_lut()
160 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc3_configure_ogam_lut()
197 static void mpc3_program_luta(struct mpc *mpc, int mpcc_id, in mpc3_program_luta() argument
62 mpc3_set_dwb_mux( struct mpc *mpc, int dwb_id, int mpcc_id) mpc3_set_dwb_mux() argument
140 mpc3_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) mpc3_power_on_ogam_lut() argument
150 mpc3_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) mpc3_configure_ogam_lut() argument
230 mpc3_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc3_program_lutb() argument
264 mpc3_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) mpc3_program_ogam_pwl() argument
320 mpc3_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) mpc3_set_output_gamma() argument
1026 program_gamut_remap( struct dcn30_mpc *mpc30, int mpcc_id, const uint16_t *regval, int select) program_gamut_remap() argument
1085 mpc3_set_gamut_remap( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust) mpc3_set_gamut_remap() argument
1314 mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx) mpcc3_acquire_rmu() argument
1333 mpcc3_release_rmu(struct mpc *mpc, int mpcc_id) mpcc3_release_rmu() argument
[all...] |
| H A D | dcn30_hwseq.c | 94 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut() local
122 if (mpcc_id_projected != mpcc_id) in dcn30_set_mpc_shaper_3dlut()
124 /*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/ in dcn30_set_mpc_shaper_3dlut()
125 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
135 /*loop through the available mux and release the requested mpcc_id*/ in dcn30_set_mpc_shaper_3dlut()
136 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
189 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func() local
213 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn30_set_output_transfer_func()
|
| H A D | dcn30_resource.h | 73 int mpcc_id,
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | mpc.h | 121 int mpcc_id; /* MPCC physical instance */ member
178 * [in] mpcc_id - The MPCC physical instance to use for blending.
189 int mpcc_id);
217 unsigned int mpcc_id);
225 * [in] mpcc_id - The MPCC physical instance.
232 int mpcc_id);
263 * [in] mpcc_id - The MPCC physical instance to use for blending.
274 int mpcc_id);
300 void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
327 int mpcc_id,
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_hwseq.c | 313 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
423 int mpcc_id, dpp_id; in dcn201_update_mpcc() local
478 mpcc_id = dpp_id; in dcn201_update_mpcc()
482 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
483 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn201_update_mpcc()
504 dc->res_pool->mpc, mpcc_id); in dcn201_update_mpcc()
507 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
514 mpcc_id); in dcn201_update_mpcc()
518 hubp->mpcc_id = mpcc_id; in dcn201_update_mpcc()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 568 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence()
686 params->update_visual_confirm_params.mpcc_id); in hwss_execute_sequence()
757 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; in hwss_power_on_mpc_mem_pwr() local
761 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on); in hwss_power_on_mpc_mem_pwr()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_hubp.c | 110 hubp2->base.mpcc_id = 0xf; in hubp31_construct()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | hw_sequencer.h | 114 int mpcc_id; member
119 int mpcc_id; member
398 int mpcc_id);
|